现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素...现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素”精度,可以有效地提高运动补偿预测准确度,为了得到“分像素”位置的像素值,需要参考其周围相邻的像素值进行插值滤波.文中提出了一种低空间复杂度1/4像素插值方法两步四抽头插值法(Two Steps Four Taps Interpolation,TSFT),该方法与目前国际上最先进的视频编码标准H.264/AVC相比,可以降低11%的空间复杂度,计算复杂度和编码效率相当,已经被国内制定的编码标准AVS1.0采纳.另外,分像素插值是解码端主要的访存和计算瓶颈,文中给出了一个基于多级流水线结构的VLSI实现结构,可以降低访存带宽,同时提高插值器的运算速度,满足高清视频实时解码的需要.展开更多
In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and...In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.展开更多
文摘现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素”精度,可以有效地提高运动补偿预测准确度,为了得到“分像素”位置的像素值,需要参考其周围相邻的像素值进行插值滤波.文中提出了一种低空间复杂度1/4像素插值方法两步四抽头插值法(Two Steps Four Taps Interpolation,TSFT),该方法与目前国际上最先进的视频编码标准H.264/AVC相比,可以降低11%的空间复杂度,计算复杂度和编码效率相当,已经被国内制定的编码标准AVS1.0采纳.另外,分像素插值是解码端主要的访存和计算瓶颈,文中给出了一个基于多级流水线结构的VLSI实现结构,可以降低访存带宽,同时提高插值器的运算速度,满足高清视频实时解码的需要.
基金This work was supported in part by the National Natural Science Foundation of China ( Grant No.69973039) and National Science Foundation of USA (Grant No. 9988441) .
文摘In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.
