设计实现了一款小型化便携式UHF RFID读写器。采用Impinj公司的射频收发芯片R1000作为核心芯片,并结合电源管理模块、ARM7及其外围电路的设计,实现工作频率为860MHz～960MHz软件可调,可兼容EPC global Gen2和ISO18000-6C两种标准。在8dB...设计实现了一款小型化便携式UHF RFID读写器。采用Impinj公司的射频收发芯片R1000作为核心芯片,并结合电源管理模块、ARM7及其外围电路的设计,实现工作频率为860MHz～960MHz软件可调,可兼容EPC global Gen2和ISO18000-6C两种标准。在8dBi天线下,该读写器实现3m以上的读写距离,并且可多标签读写。展开更多
A low cost fully integrated single-chip UHF radio frequency identification（RFID） reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a...A low cost fully integrated single-chip UHF radio frequency identification（RFID） reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is-60 dBm.The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW.The chip has a die area of 5.1×3.8 mm^2 including pads.展开更多
A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an ...A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.展开更多
A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a ...A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.展开更多
文摘设计实现了一款小型化便携式UHF RFID读写器。采用Impinj公司的射频收发芯片R1000作为核心芯片,并结合电源管理模块、ARM7及其外围电路的设计,实现工作频率为860MHz～960MHz软件可调,可兼容EPC global Gen2和ISO18000-6C两种标准。在8dBi天线下,该读写器实现3m以上的读写距离,并且可多标签读写。
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA04A102).
文摘A low cost fully integrated single-chip UHF radio frequency identification（RFID） reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is-60 dBm.The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW.The chip has a die area of 5.1×3.8 mm^2 including pads.
基金Project supported by the National High Technology Research and Development Program of China (Nos.2006AA04A109,2008AA010708)
文摘A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.
文摘A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.
