Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-sca...Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and展开更多
In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a...In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.展开更多
A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of therm...A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermalstress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results（＆lt; ±5%）. The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC, leading to the more accurate timing analysis considering the thermal-stress effect.展开更多
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient...The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.展开更多
Two innovative de-embedding methods are proposed for extracting an electrical model for a through- silicon-via （TSV） pair consisting of a ground-signal （GS） structure. In addition, based on microwave network theor...Two innovative de-embedding methods are proposed for extracting an electrical model for a through- silicon-via （TSV） pair consisting of a ground-signal （GS） structure. In addition, based on microwave network theory, a new solution scheme is developed for dealing with multiple solutions of the transfer matrix during the process of de-embedding. A unique solution is determined based on the amplitude and the phase characteristic of S parameters. In the first de-embedding method, a typical ＂π＂ type model of the TSV pair is developed, which illustrates the need to allow for frequency dependence in the equivalent TSV pair Spice model. This de-embedding method is shown to be effective for extracting the electrical properties of the TSVs. The feasibility of a second de-embedding method is also investigated.展开更多
Through-silicon vias （TSVs） have provided an attractive solution for three-dimensional （3D） integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output （I/...Through-silicon vias （TSVs） have provided an attractive solution for three-dimensional （3D） integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output （I/O） den- sity and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via （vertical interconnect access） line of a driver-TSV-load （DTL） system. The via radius and height are used to estimate the bundle aspect ratio （AR） and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 ： 1 in comparison to AR = 6：1.展开更多
A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,...A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,110μm wide vias in silicon.The wafer-level filling process can be completed in a few seconds,which is much faster than using the traditional electroplating process.Thermo-mechanical analysis of via filling using solder,Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials.It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.展开更多
Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, fo...Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.展开更多
Through-silicon via(TSV)is a key enabling technology for the emerging 3-dimension(3 D)integrated circuits(ICs).However,the crosstalk between the neighboring TSVs is one of the important sources of the soft faults.To s...Through-silicon via(TSV)is a key enabling technology for the emerging 3-dimension(3 D)integrated circuits(ICs).However,the crosstalk between the neighboring TSVs is one of the important sources of the soft faults.To suppress the crosstalk,the Fibonacci-numeral-system-based crosstalk avoidance code(FNS-CAC)is an effective scheme.Meanwhile,the self-repair schemes are often used to deal with the hard faults,but the repaired results may change the mapping between signals to TSVs,thus may reduce the crosstalk suppression ability of FNS-CAC.A TSV self-repair technique with an improved FNS-CAC codec is proposed in this work.The codec is designed based on the improved Fibonacci numeral system(FNS)adders,which are adaptive to the health states of TSVs.The proposed self-repair technique is able to suppress the crosstalk and repair the faulty TSVs simultaneously.The simulation and analysis results show that the proposed scheme keeps the crosstalk suppression ability of the original FNS-CAC,and it has higher reparability than the local self-repair schemes,such as the signal-switching-based and the signal-shifting-based counterparts.展开更多
设计了一款采用硅基板作为载体的毫米波上变频微系统系统级封装(System in Package,SiP)模块。该模块利用类同轴硅通孔(Through-Silicon-Via,TSV)结构解决了毫米波频段信号在转接板层间低损耗垂直传输的问题。该结构整体采用四层硅基板...设计了一款采用硅基板作为载体的毫米波上变频微系统系统级封装(System in Package,SiP)模块。该模块利用类同轴硅通孔(Through-Silicon-Via,TSV)结构解决了毫米波频段信号在转接板层间低损耗垂直传输的问题。该结构整体采用四层硅基板封装,并在封装完成后对硅基射频SiP模块进行了测试。测试结果显示,在工作频段29~31 GHz之间,其增益大于27 dB,端口驻波小于1.4,且带外杂散抑制大于55 dB。该毫米波硅基SiP模块具有结构简单、集成度高、射频性能良好等优点,其体积不到传统二维集成结构的5%,实现了毫米波频段模块的微系统化,可广泛运用于射频微系统。展开更多
针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D No C)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D No C测试的影响,进一步优化3D No C在测试模式下的TSV数量...针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D No C)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D No C测试的影响,进一步优化3D No C在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D No C的测试TSV数量,提高了TSV的利用率。展开更多
We describe how a direct combination of an axicon and a lens can represent a simple and efficient beam-shaping solution for laser material processing applications.We produce high-angle pseudo-Bessel micro-beams at 155...We describe how a direct combination of an axicon and a lens can represent a simple and efficient beam-shaping solution for laser material processing applications.We produce high-angle pseudo-Bessel micro-beams at 1550 nm,which would be difficult to produce by other methods.Combined with appropriate stretching of femtosecond pulses,we access optimized conditions inside semiconductors allowing us to develop high-aspect-ratio refractive-index writing methods.Using ultrafast microscopy techniques,we characterize the delivered local intensities and the triggered ionization dynamics inside silicon with 200-fs and 50-ps pulses.While similar plasma densities are produced in both cases,we show that repeated picosecond irradiation induces permanent modifications spontaneously growing shot-after-shot in the direction of the laser beam from front-surface damage to the back side of irradiated silicon wafers.The conditions for direct microexplosion and microchannel drilling similar to those today demonstrated for dielectrics still remain inaccessible.Nonetheless,this work evidences higher energy densities than those previously achieved in semiconductors and a novel percussion writing modality to create structures in silicon with aspect ratios exceeding~700 without any motion of the beam.The estimated transient change of conductivity and measured ionization fronts at near luminal speed along the observed microplasma channels support the vision of vertical electrical connections optically controllable at GHz repetition rates.The permanent silicon modifications obtained by percussion writing are light-guiding structures according to a measured positive refractive index change exceeding 10-2.These findings open the door to unique monolithic solutions for electrical and optical through-silicon-vias which are key elements for vertical interconnections in 3D chip stacks.展开更多
基金This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.
文摘Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and
基金supported by the National Key Research and Development Program of China(2021YFB2011700).
文摘In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
基金supported by the Aerospace Advanced Manufacturing Technology Research Joint Fund(No.U1537208)
文摘A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermalstress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results（＆lt; ±5%）. The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC, leading to the more accurate timing analysis considering the thermal-stress effect.
文摘The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.
基金Project supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics, Chinese Academy of Sciencessupport by 100 Talents Program(No.Y0YB049001) of Chinese Academy of Sciences
文摘Two innovative de-embedding methods are proposed for extracting an electrical model for a through- silicon-via （TSV） pair consisting of a ground-signal （GS） structure. In addition, based on microwave network theory, a new solution scheme is developed for dealing with multiple solutions of the transfer matrix during the process of de-embedding. A unique solution is determined based on the amplitude and the phase characteristic of S parameters. In the first de-embedding method, a typical ＂π＂ type model of the TSV pair is developed, which illustrates the need to allow for frequency dependence in the equivalent TSV pair Spice model. This de-embedding method is shown to be effective for extracting the electrical properties of the TSVs. The feasibility of a second de-embedding method is also investigated.
文摘Through-silicon vias （TSVs） have provided an attractive solution for three-dimensional （3D） integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output （I/O） den- sity and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via （vertical interconnect access） line of a driver-TSV-load （DTL） system. The via radius and height are used to estimate the bundle aspect ratio （AR） and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 ： 1 in comparison to AR = 6：1.
基金Project supported by the National S & T Major Projects(Nos.2009ZX02038,2011ZX02709)the 100 Talents Programme of the Chinese Academy of Sciences
文摘A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,110μm wide vias in silicon.The wafer-level filling process can be completed in a few seconds,which is much faster than using the traditional electroplating process.Thermo-mechanical analysis of via filling using solder,Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials.It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.
基金Sponsored by the National Natural Science Foundation of China(No.61271149)
文摘Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.
基金supported in part by the Key-Area Research and Development Program of Guangdong Province(2019B010155002)the National Key Research and Development Project(2018YFB2202600)the Research and Development Project of Shenzhen Government(ZDSYS201802061805105).
文摘Through-silicon via(TSV)is a key enabling technology for the emerging 3-dimension(3 D)integrated circuits(ICs).However,the crosstalk between the neighboring TSVs is one of the important sources of the soft faults.To suppress the crosstalk,the Fibonacci-numeral-system-based crosstalk avoidance code(FNS-CAC)is an effective scheme.Meanwhile,the self-repair schemes are often used to deal with the hard faults,but the repaired results may change the mapping between signals to TSVs,thus may reduce the crosstalk suppression ability of FNS-CAC.A TSV self-repair technique with an improved FNS-CAC codec is proposed in this work.The codec is designed based on the improved Fibonacci numeral system(FNS)adders,which are adaptive to the health states of TSVs.The proposed self-repair technique is able to suppress the crosstalk and repair the faulty TSVs simultaneously.The simulation and analysis results show that the proposed scheme keeps the crosstalk suppression ability of the original FNS-CAC,and it has higher reparability than the local self-repair schemes,such as the signal-switching-based and the signal-shifting-based counterparts.
文摘针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D No C)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D No C测试的影响,进一步优化3D No C在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D No C的测试TSV数量,提高了TSV的利用率。
基金conducted using LaMP facilities at LP3.The project received funding from the French National Research Agency(ANR-22-CE92-0057-0,KiSS project)and the European Union’s Horizon 2020 research and innovation program under grant agreements No.101034324(MSCA-COFUND)and No.724480(ERC).
文摘We describe how a direct combination of an axicon and a lens can represent a simple and efficient beam-shaping solution for laser material processing applications.We produce high-angle pseudo-Bessel micro-beams at 1550 nm,which would be difficult to produce by other methods.Combined with appropriate stretching of femtosecond pulses,we access optimized conditions inside semiconductors allowing us to develop high-aspect-ratio refractive-index writing methods.Using ultrafast microscopy techniques,we characterize the delivered local intensities and the triggered ionization dynamics inside silicon with 200-fs and 50-ps pulses.While similar plasma densities are produced in both cases,we show that repeated picosecond irradiation induces permanent modifications spontaneously growing shot-after-shot in the direction of the laser beam from front-surface damage to the back side of irradiated silicon wafers.The conditions for direct microexplosion and microchannel drilling similar to those today demonstrated for dielectrics still remain inaccessible.Nonetheless,this work evidences higher energy densities than those previously achieved in semiconductors and a novel percussion writing modality to create structures in silicon with aspect ratios exceeding~700 without any motion of the beam.The estimated transient change of conductivity and measured ionization fronts at near luminal speed along the observed microplasma channels support the vision of vertical electrical connections optically controllable at GHz repetition rates.The permanent silicon modifications obtained by percussion writing are light-guiding structures according to a measured positive refractive index change exceeding 10-2.These findings open the door to unique monolithic solutions for electrical and optical through-silicon-vias which are key elements for vertical interconnections in 3D chip stacks.
