Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vert...Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.展开更多
三维集成电路(three dimensional integrated circuit,3DIC)和片上网络(network on chip,NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip,3DNoC)是当前研究的热点之一.针对现有3DNoC...三维集成电路(three dimensional integrated circuit,3DIC)和片上网络(network on chip,NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip,3DNoC)是当前研究的热点之一.针对现有3DNoC的研究没有充分关注硅片内与硅片间的异构通信特征.提出了面向通信特征的硅片间单跳步(single hop inter dies,SHID)体系结构,该结构采用异构拓扑结构和硅片间扩展路由器(express inter dies router,EIDR).通过实验数据的分析表明,与3DMesh和NoC-Bus这两种已有的3DNoC结构相比,SHID结构有以下特点:1)延迟较低,4层堆叠时比3D-Mesh低15.1%,比NoC-Bus低11.5%;2)功耗与NoC-Bus相当,比3D-Mesh低10%左右;3)吞吐率随堆叠层数增加下降缓慢,16层堆叠时吞吐率比3D-Mesh高66.98%,比NoC-Bus高314.49%.SHID体系结构同时具备性能和可扩展性的优势,是未来3DNoC体系结构良好设计选择.展开更多
This paper introduces a new three dimensional autonomous system with five equilibrium points. It demonstrates complex chaotic behaviours within a wide range of parameters, which are described by phase portraits, Lyapu...This paper introduces a new three dimensional autonomous system with five equilibrium points. It demonstrates complex chaotic behaviours within a wide range of parameters, which are described by phase portraits, Lyapunov exponents, frequency spectrum, etc. Analysis of the bifurcation and Poincar@ map is used to reveal mechanisms of generating these complicated phenomena. The corresponding electronic circuits are designed, exhibiting experimental chaotic attractors in accord with numerical simulations. Since frequency spectrum analysis shows a broad frequency bandwidth, this system has perspective of potential applications in such engineering fields as secure communication.展开更多
基金Supported by the National Natural Science Foundation of China (Nos.60833004 and 60876026)the 3-D Floorplanning and Placement Project of the Intel Corporation
文摘Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.
文摘三维集成电路(three dimensional integrated circuit,3DIC)和片上网络(network on chip,NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip,3DNoC)是当前研究的热点之一.针对现有3DNoC的研究没有充分关注硅片内与硅片间的异构通信特征.提出了面向通信特征的硅片间单跳步(single hop inter dies,SHID)体系结构,该结构采用异构拓扑结构和硅片间扩展路由器(express inter dies router,EIDR).通过实验数据的分析表明,与3DMesh和NoC-Bus这两种已有的3DNoC结构相比,SHID结构有以下特点:1)延迟较低,4层堆叠时比3D-Mesh低15.1%,比NoC-Bus低11.5%;2)功耗与NoC-Bus相当,比3D-Mesh低10%左右;3)吞吐率随堆叠层数增加下降缓慢,16层堆叠时吞吐率比3D-Mesh高66.98%,比NoC-Bus高314.49%.SHID体系结构同时具备性能和可扩展性的优势,是未来3DNoC体系结构良好设计选择.
基金supported by the National Natural Science Foundation of China (Grant No. 10771088)Natural Science Foundation of Jiangsu Province,China (Grant No. 2007098)+3 种基金Outstanding Personnel Program in Six Fields of Jiangsu Province,China (Grant No. 6-A-029)National Natural Science (Youth) Foundation of China (Grant No. 10801140)Youth Foundation of Chongqing Normal University,China (Grant No. 08XLQ04)the Natural Science Foundation of the Jiangsu Higher Education Institutions of China (Grant No. 09B 202Z)
文摘This paper introduces a new three dimensional autonomous system with five equilibrium points. It demonstrates complex chaotic behaviours within a wide range of parameters, which are described by phase portraits, Lyapunov exponents, frequency spectrum, etc. Analysis of the bifurcation and Poincar@ map is used to reveal mechanisms of generating these complicated phenomena. The corresponding electronic circuits are designed, exhibiting experimental chaotic attractors in accord with numerical simulations. Since frequency spectrum analysis shows a broad frequency bandwidth, this system has perspective of potential applications in such engineering fields as secure communication.
