We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain ...We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.展开更多
For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute devic...For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.展开更多
We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the p...We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.展开更多
We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage）...We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.展开更多
A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poi...A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.展开更多
This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a p...This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.展开更多
A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potenti...A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor（Si-DG TFET） is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed（as in the case of the DG MOSFET）; instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential（e QFP）decreases as the channel potential starts to decrease, and there are hiphops in the channel e QFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I–V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.展开更多
A PNPN tunnel field effect transistor（TFET） with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET＇s performance were investigated t...A PNPN tunnel field effect transistor（TFET） with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET＇s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.展开更多
In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. I...In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.展开更多
Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially ...Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density Ion of the proposed TFET can be as large as 3.4 × 10^−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of Ion and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10^−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.展开更多
A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region(InN-Hetero-TG-TFET)is proposed and investigated by Silvaco-Atlas simulations for the...A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region(InN-Hetero-TG-TFET)is proposed and investigated by Silvaco-Atlas simulations for the first time.Compared with the conventional physical doping TFET devices,the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively,which could provide an effective solution of random dopant fluctuation(RDF)and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping.Besides,due to the hetero T-shaped gate,the improvement of the on-state performance can be achieved in the proposed device.The simulations of the device proposed here in this work show ION of 4.45×10^(-5)A/μm,ION/IOFF ratio of 10^(13),and SS_(avg)of 7.5 mV/dec in InN-Hetero-TG-TFET,which are better than the counterparts of the device with a homo T-shaped gate(InN-Homo-TG-TFET)and our reported lateral polarization-induced InN-based TFET(PI-InN-TFET).These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications.展开更多
We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The mod...We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.展开更多
The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characte...The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.展开更多
To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the infl...To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.展开更多
文摘We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.
文摘For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
文摘We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.
文摘We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the Graduate Innovation Fund of Anhui University
文摘A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
基金supported by Women Scientist Scheme-A, Department of Science and Technology, New Delhi, Government of India, under the Grant SR/WOS-A/ET-5/2017
文摘This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.
文摘A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor（Si-DG TFET） is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed（as in the case of the DG MOSFET）; instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential（e QFP）decreases as the channel potential starts to decrease, and there are hiphops in the channel e QFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I–V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.
基金Project supported by the State Key Development Program for Basic Research of China(No.2011CBA00602)the National Natural Science Foundation of China(Nos.60876076,60976013,60820106001)
文摘A PNPN tunnel field effect transistor（TFET） with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET＇s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.
文摘In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.
基金Project supported by the National Natural Science Foundation of China(Grant No.61704130)the Science Research Plan in Shaanxi Province,China(Grant No.2018JQ6064)the Science and Technology Project on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C029).
文摘Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density Ion of the proposed TFET can be as large as 3.4 × 10^−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of Ion and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10^−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.
基金the Key Research and Development Program of Shaanxi Province,China(Grant No.2020ZDLGY03-05)the National Natural Science Foundation of China(Grant No.61574112).
文摘A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region(InN-Hetero-TG-TFET)is proposed and investigated by Silvaco-Atlas simulations for the first time.Compared with the conventional physical doping TFET devices,the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively,which could provide an effective solution of random dopant fluctuation(RDF)and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping.Besides,due to the hetero T-shaped gate,the improvement of the on-state performance can be achieved in the proposed device.The simulations of the device proposed here in this work show ION of 4.45×10^(-5)A/μm,ION/IOFF ratio of 10^(13),and SS_(avg)of 7.5 mV/dec in InN-Hetero-TG-TFET,which are better than the counterparts of the device with a homo T-shaped gate(InN-Homo-TG-TFET)and our reported lateral polarization-induced InN-based TFET(PI-InN-TFET).These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications.
文摘We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.
文摘The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.
基金Project supported by the Key Research and Development Program of Shaanxi(Grant No.2021GY-010)the National Defense Science and Technology Foundation Strengthening Program of China(Grant No.2019-XXXX-XX-236-00).
文摘To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.
