Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control tec...Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.展开更多
In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack t...In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.展开更多
We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （perfor...We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.展开更多
A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and st...A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.展开更多
文摘Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
文摘In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.
文摘We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.
基金supported by the China State-Funded Study Abroad Program for High-Level Universities
文摘A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.
