提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进...提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外，在电路中加入了省电模式，可在保持LDO输出1．8V情况下节省大于70％的功耗。该设计采用HHNEC0．13μmCMOS工艺，仿真结果显示：在2．5～5．5V电源供电、各个工艺角及温度变化条件下，LDO输出的线性调整率小于2．3mV／V，负载调整率小于14μV／mA，温度系数小于27×10^-6／℃；在正常工作模式下，整个LDO消耗85μA电流；在省电模式下仅消耗23斗A电流。展开更多
In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack t...In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.展开更多
NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-p...NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.展开更多
提出了一种改进的高输入电压调整电路结构,该电路结构在TSMC 0.25μm BCD工艺平台进行验证。电路包括两个参考电压模块、两级调整电路和一个关断信号产生模块。介绍了初级电压调整和精确电压调整电路,可以产生稳定精确的输出电压,同时...提出了一种改进的高输入电压调整电路结构,该电路结构在TSMC 0.25μm BCD工艺平台进行验证。电路包括两个参考电压模块、两级调整电路和一个关断信号产生模块。介绍了初级电压调整和精确电压调整电路,可以产生稳定精确的输出电压,同时也提高了低输入电源电压时的输出电流能力。通过两级电源调整电路可以实现软启动功能,减小启动浪涌电压,提高启动性能。此外,关断模块产生可以可靠关闭高压模块和低压模块的两种控制信号,使得在待机模式下高压直流转换系统仅消耗极低的待机电流。该电路结构的输入电压可以在2.5~45 V宽幅范围内变化。在待机模式下,高压直流转换系统的待机电流最低仅300 n A,电源调整电路可以输出最高60 m A的负载电流。展开更多
文摘提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外，在电路中加入了省电模式，可在保持LDO输出1．8V情况下节省大于70％的功耗。该设计采用HHNEC0．13μmCMOS工艺，仿真结果显示：在2．5～5．5V电源供电、各个工艺角及温度变化条件下，LDO输出的线性调整率小于2．3mV／V，负载调整率小于14μV／mA，温度系数小于27×10^-6／℃；在正常工作模式下，整个LDO消耗85μA电流；在省电模式下仅消耗23斗A电流。
文摘In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.
基金supported by the National Natural Science Foundation of China(Nos.61274036,61106038,61371025)the Doctoral Fund of Ministry of Education of China(No.20110111120012)
文摘NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.
文摘提出了一种改进的高输入电压调整电路结构,该电路结构在TSMC 0.25μm BCD工艺平台进行验证。电路包括两个参考电压模块、两级调整电路和一个关断信号产生模块。介绍了初级电压调整和精确电压调整电路,可以产生稳定精确的输出电压,同时也提高了低输入电源电压时的输出电流能力。通过两级电源调整电路可以实现软启动功能,减小启动浪涌电压,提高启动性能。此外,关断模块产生可以可靠关闭高压模块和低压模块的两种控制信号,使得在待机模式下高压直流转换系统仅消耗极低的待机电流。该电路结构的输入电压可以在2.5~45 V宽幅范围内变化。在待机模式下,高压直流转换系统的待机电流最低仅300 n A,电源调整电路可以输出最高60 m A的负载电流。
