Investigators are attracted by the complexity and significance of preventive maintenance problem,and there are hundreds of maintenance models and methods to solve the maintenance problems of companies and army,going w...Investigators are attracted by the complexity and significance of preventive maintenance problem,and there are hundreds of maintenance models and methods to solve the maintenance problems of companies and army,going with a lot of investigative harvests. However,one-component system or series system is focused by most of the literature.The problem of preventive maintenance（PM） on cold standby repairable system does not attach importance despite the fact that the cold standby repairable system is ubiquitous in engineering systems.In this paper,an optimal replacement model for gamma deteriorating system is studied.This methodology presented uses a gamma distribution to model the material degradation,and the impact of imperfect maintenance actions on system reliability is investigated.After an imperfect maintenance action,the state of a degrading system is assumed as a random variable and the maintenance time follows a geometric process.A maintenance policy（N）is applied by which the system will be repaired whenever it experiences the Nth PM,and an optimal policy（N~＊） could be determined numerically or analytically for minimizing the long-run average cost per unit time.A numerical example about how to confirm the optimal maintenance time by the inspecting information of liquid coupling device is given to demonstrate the use of this policy.This paper presents a condition-based replacement policy for cold standby repairable system under continuous monitoring.Its contribution embody in two aspects,relaxing the restrictions of hypothesis and investigating the condition-based maintenance policy of the cold standby repairable system which is ignored by others.展开更多
Structures of monotone systems and cold standby systems with exponen-tial life distributions and dependent components are studied. It is shown that a mono-tone system composed of components with multivariate HNBUE lif...Structures of monotone systems and cold standby systems with exponen-tial life distributions and dependent components are studied. It is shown that a mono-tone system composed of components with multivariate HNBUE life distributions isessentially a series system composed of components with multivariate exponential lifedistributions. Also, it is proved that for cold standby systems composed of componentswith multivariate NBU life distributions, all but oue of the components are degenerateat zero while the remaining one is exponential. In addition, several equivalent char-acterizations of multivariate exponential distribution are provided in the multivariateHNBUE life distribution class which include many existing results as special cases.展开更多
To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it i...To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.展开更多
This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V proces...This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.展开更多
This paper investigates a warm standby repairable retrial system with two types of components and a single reparman,where type 1 components have priority over type 2 in use.Failure and repair times for each type of co...This paper investigates a warm standby repairable retrial system with two types of components and a single reparman,where type 1 components have priority over type 2 in use.Failure and repair times for each type of component are assumed to be exponential distributions.The retrial feature is considered and the retrial time of each failed component is exponentially distributed.By using Markov process theory and matrix analytic method,the system steady-state probabil-ities are derived,and the system steady-state availability and some steady-state performance indices are obtained.Using the Bayesian approach,the system parameters can be estimated.The cost-benefit ratio function of the system is constructed based on the failed components and repairman's states.Numerical experiments are given to evaluate the effect of each parameter on the system steady-state availability and optimize the system cost-benefit ratio with repair rate as a decision variable.展开更多
随着财务系统数据库的使用时间增长,数据库中的数据量也会增加,数据量越大也意味着数据库备份与恢复所需要的成本就越高,不仅是备份所需时间越来越长,恢复数据所需时间也随之增长;当数据库发生意外而导致数据库中的数据不可修复的时候,...随着财务系统数据库的使用时间增长,数据库中的数据量也会增加,数据量越大也意味着数据库备份与恢复所需要的成本就越高,不仅是备份所需时间越来越长,恢复数据所需时间也随之增长;当数据库发生意外而导致数据库中的数据不可修复的时候,容灾远比备份更能快速有效的恢复生产业务的数据;在实际的使用过程中,我们也可以把容灾当做是一个活动的备份来使用,主要介绍了Oracle Data Guard和GoldenGate。展开更多
Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control tec...Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.展开更多
By using Bayesian and multiple Bayesian method, the failure probability, reliability and mean time to failure(MTTF) of series system with cold standby units are estimated. At last, we compare the two estimators by mea...By using Bayesian and multiple Bayesian method, the failure probability, reliability and mean time to failure(MTTF) of series system with cold standby units are estimated. At last, we compare the two estimators by means of Monte_Carlo simulation.展开更多
基金supported by National Natural Science Foundation of China(Grant No.60904002)
文摘Investigators are attracted by the complexity and significance of preventive maintenance problem,and there are hundreds of maintenance models and methods to solve the maintenance problems of companies and army,going with a lot of investigative harvests. However,one-component system or series system is focused by most of the literature.The problem of preventive maintenance（PM） on cold standby repairable system does not attach importance despite the fact that the cold standby repairable system is ubiquitous in engineering systems.In this paper,an optimal replacement model for gamma deteriorating system is studied.This methodology presented uses a gamma distribution to model the material degradation,and the impact of imperfect maintenance actions on system reliability is investigated.After an imperfect maintenance action,the state of a degrading system is assumed as a random variable and the maintenance time follows a geometric process.A maintenance policy（N）is applied by which the system will be repaired whenever it experiences the Nth PM,and an optimal policy（N~＊） could be determined numerically or analytically for minimizing the long-run average cost per unit time.A numerical example about how to confirm the optimal maintenance time by the inspecting information of liquid coupling device is given to demonstrate the use of this policy.This paper presents a condition-based replacement policy for cold standby repairable system under continuous monitoring.Its contribution embody in two aspects,relaxing the restrictions of hypothesis and investigating the condition-based maintenance policy of the cold standby repairable system which is ignored by others.
基金This work is supported by the Natural Science Foundation of the Jiangsu Provincial Education Commission.
文摘Structures of monotone systems and cold standby systems with exponen-tial life distributions and dependent components are studied. It is shown that a mono-tone system composed of components with multivariate HNBUE life distributions isessentially a series system composed of components with multivariate exponential lifedistributions. Also, it is proved that for cold standby systems composed of componentswith multivariate NBU life distributions, all but oue of the components are degenerateat zero while the remaining one is exponential. In addition, several equivalent char-acterizations of multivariate exponential distribution are provided in the multivariateHNBUE life distribution class which include many existing results as special cases.
文摘To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.
文摘This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.
基金This work was supported by the National Natural Science Foundation of China[Grant Number 72071175,72001070].
文摘This paper investigates a warm standby repairable retrial system with two types of components and a single reparman,where type 1 components have priority over type 2 in use.Failure and repair times for each type of component are assumed to be exponential distributions.The retrial feature is considered and the retrial time of each failed component is exponentially distributed.By using Markov process theory and matrix analytic method,the system steady-state probabil-ities are derived,and the system steady-state availability and some steady-state performance indices are obtained.Using the Bayesian approach,the system parameters can be estimated.The cost-benefit ratio function of the system is constructed based on the failed components and repairman's states.Numerical experiments are given to evaluate the effect of each parameter on the system steady-state availability and optimize the system cost-benefit ratio with repair rate as a decision variable.
文摘随着财务系统数据库的使用时间增长,数据库中的数据量也会增加,数据量越大也意味着数据库备份与恢复所需要的成本就越高,不仅是备份所需时间越来越长,恢复数据所需时间也随之增长;当数据库发生意外而导致数据库中的数据不可修复的时候,容灾远比备份更能快速有效的恢复生产业务的数据;在实际的使用过程中,我们也可以把容灾当做是一个活动的备份来使用,主要介绍了Oracle Data Guard和GoldenGate。
文摘Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
文摘By using Bayesian and multiple Bayesian method, the failure probability, reliability and mean time to failure(MTTF) of series system with cold standby units are estimated. At last, we compare the two estimators by means of Monte_Carlo simulation.
