A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output match...A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm × 495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance： a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved; the input and output return losses were better than - 10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OPtdB and OIP3 were 1.7 dBm and 11 dBm at 3-dB bandwidth, respectively.展开更多
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2009ZX02303-003)
文摘A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm × 495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance： a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved; the input and output return losses were better than - 10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OPtdB and OIP3 were 1.7 dBm and 11 dBm at 3-dB bandwidth, respectively.
文摘为了在兼顾特征频率(fT)和电流增益(β)的情况下有效提高器件的击穿电压(BVCBO/BVCEO),利用SILVACO TCAD建立了npn型超结集电区Si Ge异质结双极晶体管(heterojunction bipolar transistor,HBT)的器件模型.研究表明:通过在集电结空间电荷区(collector-base space charge region,CB SCR)内引入p型超结层可有效降低"死区"内的电场强度,使较高的电场强度转移至"死区"外较深的CB SCR内,进而在几乎不增加CB SCR宽度的情况下抑制碰撞电离,达到提高击穿电压、改善fT和β的目的.随着p型超结层厚度(dp)的增加,击穿电压BVCBO和BVCEO的改善也越明显.但dp值需优化,较大的dp值将引发Kirk效应,大幅降低器件的fT和β.进一步通过优化p型超结层的dp值,设计出一款dp为0.2μm且具有高频高压大电流优值(fT×BVCEO×β)的新型超结集电区Si Ge HBT.结果表明:与传统Si Ge HBT相比,新器件的fT×BVCEO×β优值改善高达35.5%,有效拓展了功率Si Ge HBT的高压大电流工作范围.
