结合国内现有的加工工艺水平,提出自偏置条件下的反向并联二极管对电路结构.不但解决了三倍频器偏置电路加工的难题,而且可以有效实现奇次倍频.同时,利用HFSS和ADS软件,以场路结合的方式准确模拟三倍频器的电特性,考虑到寄生参数引入的...结合国内现有的加工工艺水平,提出自偏置条件下的反向并联二极管对电路结构.不但解决了三倍频器偏置电路加工的难题,而且可以有效实现奇次倍频.同时,利用HFSS和ADS软件,以场路结合的方式准确模拟三倍频器的电特性,考虑到寄生参数引入的影响.设计完成以后,器件加工以及电装过程均在国内完成.测试结果表明在221 GHz处,有最大输出功率3.1 m W,在219~227 GHz频率范围内输出功率均大于2 m W.以上研究为今后设计高效率亚毫米波倍频器提供重要的参考价值.展开更多
A 20 GHz-24 GHz three-stage low noise amplifier(LNA) was implemented using the GaAs pseudomorphic high electron mobility transistor(PHEMT) process. The schematic design and optimization of the LNA were carried out usi...A 20 GHz-24 GHz three-stage low noise amplifier(LNA) was implemented using the GaAs pseudomorphic high electron mobility transistor(PHEMT) process. The schematic design and optimization of the LNA were carried out using advanced design system(ADS). The three-stage series structure is used to increase the gain of the amplifier. Additionally, a self-biasing network and negative feedback circuit can expand the bandwidth while increasing the stability of the circuit and obtaining better input matching and noise. The test results show that the gain in the 20 GHz-24 GHz band is greater than 20 dB, the noise figure(NF) is 2.1 dB, and the input and output reflection coefficients are less than-10 dB, which meets the design requirements. The amplifier serves a wide range of applications, including wireless communications, radar systems, satellite communications, and other areas that require high-frequency amplification to enhance system performance and sensitivity.展开更多
A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
文摘结合国内现有的加工工艺水平,提出自偏置条件下的反向并联二极管对电路结构.不但解决了三倍频器偏置电路加工的难题,而且可以有效实现奇次倍频.同时,利用HFSS和ADS软件,以场路结合的方式准确模拟三倍频器的电特性,考虑到寄生参数引入的影响.设计完成以后,器件加工以及电装过程均在国内完成.测试结果表明在221 GHz处,有最大输出功率3.1 m W,在219~227 GHz频率范围内输出功率均大于2 m W.以上研究为今后设计高效率亚毫米波倍频器提供重要的参考价值.
文摘A 20 GHz-24 GHz three-stage low noise amplifier(LNA) was implemented using the GaAs pseudomorphic high electron mobility transistor(PHEMT) process. The schematic design and optimization of the LNA were carried out using advanced design system(ADS). The three-stage series structure is used to increase the gain of the amplifier. Additionally, a self-biasing network and negative feedback circuit can expand the bandwidth while increasing the stability of the circuit and obtaining better input matching and noise. The test results show that the gain in the 20 GHz-24 GHz band is greater than 20 dB, the noise figure(NF) is 2.1 dB, and the input and output reflection coefficients are less than-10 dB, which meets the design requirements. The amplifier serves a wide range of applications, including wireless communications, radar systems, satellite communications, and other areas that require high-frequency amplification to enhance system performance and sensitivity.
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
