According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analy...According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.展开更多
As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs ca...As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPCA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.展开更多
SRAM-based FPGA devices are irradiated by ^（60）Coγrays at various aose rates 10 investigate total dose effects and the evaluation method.The dependences of typical electrical parameters such as static power current...SRAM-based FPGA devices are irradiated by ^（60）Coγrays at various aose rates 10 investigate total dose effects and the evaluation method.The dependences of typical electrical parameters such as static power current, peak-peak value,and delay time on total dose are discussed.The experiment results show that the static power current of the devices reduces rapidly at room temperature（25℃） and high temperature（80℃） annealing after irradiation.When the device is irradiated at a low dose rate,the delay time and peak-peak value change unobviously with an increase in the accumulated dose.In contrast,the function parameters completely fail at 2.1 kGy（Si） when the dose rate increases to 0.71 Gy（Si）/s.展开更多
SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As ...SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.展开更多
基金supported by the National High Technology Research and Development Program of China ("863" Program) (Grant No. 2006SQ710375)the Civil Aerospace Technologies Advanced Research Pro-gram of China (Grant No. C1320061301)Ministries and Commissions’Advanced Research Found of China (Grant No. 9140A20070209KG0160)
文摘According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.
文摘As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPCA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.
文摘SRAM-based FPGA devices are irradiated by ^（60）Coγrays at various aose rates 10 investigate total dose effects and the evaluation method.The dependences of typical electrical parameters such as static power current, peak-peak value,and delay time on total dose are discussed.The experiment results show that the static power current of the devices reduces rapidly at room temperature（25℃） and high temperature（80℃） annealing after irradiation.When the device is irradiated at a low dose rate,the delay time and peak-peak value change unobviously with an increase in the accumulated dose.In contrast,the function parameters completely fail at 2.1 kGy（Si） when the dose rate increases to 0.71 Gy（Si）/s.
基金Project supported by the National Natural Science Foundation of China(No.10875096).
文摘SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.
