Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector....Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage （GSS）, elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form （MMPRMF） starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.展开更多
By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM funct...By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset table.Furthermore,by employing the multiplexer model,the algorithm is extended to optimize multi-level multi-output mixed-polarity RM forms.The proposed algorithm is implemented in C language and tested using some MCNC benchmarks.Experimental results show that the proposed algorithm can obtain a more compact RM form than that under fixed polarity.Compared with published results,the proposed algorithm makes a significant speed improvement,with a small increase in the number of literals.展开更多
This paper discusses the definitions and properties of two kinds of fundamental symmetric functions, which are based on AND-OR-NOT algebraic system and AND-Exclusive OR algebraic system, respectively. Based upon it, s...This paper discusses the definitions and properties of two kinds of fundamental symmetric functions, which are based on AND-OR-NOT algebraic system and AND-Exclusive OR algebraic system, respectively. Based upon it, some mapping transformation methods between two kinds of expansion coefficients of an arbitrary symmetric, function in the complete set of two fundamental symmetric functions.展开更多
Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modem devices and new design methods. The thr...Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modem devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode （RTD） is well suited for imple- menting the threshold logic gate because of its high-speed switching capability, negative differential resistance （NDR） charac- teristic, and functional versatility. In this paper, based on the Reed-Muller （RM） algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a program- mable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate （ULG3） is proposed, composed of two RTD-based universal threshold logic gates （UTLG） and an RTD-based three-variable XOR gate （XOR3）. The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.展开更多
文摘Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage （GSS）, elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form （MMPRMF） starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.
基金Project supported by the National Natural Science Foundation of China (Nos.60871022 and 61041001)the Natural Science Foundation of Zhejiang Province (Nos.Z1090622 and Y1080654)the Ningbo Natural Science Foundation,China (No.2010A610183)
文摘By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset table.Furthermore,by employing the multiplexer model,the algorithm is extended to optimize multi-level multi-output mixed-polarity RM forms.The proposed algorithm is implemented in C language and tested using some MCNC benchmarks.Experimental results show that the proposed algorithm can obtain a more compact RM form than that under fixed polarity.Compared with published results,the proposed algorithm makes a significant speed improvement,with a small increase in the number of literals.
文摘This paper discusses the definitions and properties of two kinds of fundamental symmetric functions, which are based on AND-OR-NOT algebraic system and AND-Exclusive OR algebraic system, respectively. Based upon it, some mapping transformation methods between two kinds of expansion coefficients of an arbitrary symmetric, function in the complete set of two fundamental symmetric functions.
基金supported by the National Natural Science Foundation of China(Nos.61271124 and 61471314)the Zhejiang Provincial Natural Science Foundation of China(Nos.LY13F010001 and LY15F010011)
文摘Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modem devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode （RTD） is well suited for imple- menting the threshold logic gate because of its high-speed switching capability, negative differential resistance （NDR） charac- teristic, and functional versatility. In this paper, based on the Reed-Muller （RM） algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a program- mable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate （ULG3） is proposed, composed of two RTD-based universal threshold logic gates （UTLG） and an RTD-based three-variable XOR gate （XOR3）. The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.
