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Quad-Level Cell NAND Design and Soft-Bit Generation for Low-Density Parity-Check Decoding in System-Level Application
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作者 LIU Shijun ZOU Xuecheng WANG Baocun 《Wuhan University Journal of Natural Sciences》 CAS CSCD 2018年第1期70-78,共9页
QLC(Quad-Level Cell) NAND flash will be one of the future technologies for next generation memory chip after three-dimensional(3D) TLC(Triple-Level Cell) stacked NAND flash. In QLC device, data errors will easil... QLC(Quad-Level Cell) NAND flash will be one of the future technologies for next generation memory chip after three-dimensional(3D) TLC(Triple-Level Cell) stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on "half-change" Gray coding are researched. Because of the probable error impact of QLC NAND cell's voltage change, the solution of generating the soft information after XOR(exclusive OR) the soft bits by internal read mechanism is presented for Low-Density Parity-Check(LDPC) Belief Propagation(BP) decoding in QLC design for its system level application. 展开更多
关键词 qlc quad-level cellnand error-correcting code(ECC) Low-Density Parity-Check (LDPC) Soft-Bit Generation
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