When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the ...When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low h...The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.展开更多
In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are de...In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are derived by permuting the matrices of the corresponding RC-LDPC block codes,are systematic and have maximum encoding memory.Simulation results show that the proposed RC-LDPC convolutional codes with belief propagation(BP) decoding collectively offer a steady improvement on performance compared with the block counterparts over the binary-input additive white Gaussian noise channels(BI-AWGNCs).展开更多
Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper ...Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.展开更多
The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for dec...The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for decoding LDPC codes that includes a slight increase in computational complexity.The MLP decoder adaptively adds new constraints which are compatible with a selected check node to refine the results when an error is reported by the original LP decoder.The MLP decoder result is shown to have the maximum-likelihood（ML） certificate property.Simulations with moderate block length LDPC codes suggest that the MLP decoder gives better performance than both the original LP decoder and the conventional sum-product（SP） decoder.展开更多
An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the ...An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.展开更多
Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to re...Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.展开更多
This letter proposes a novel and simple construction of regular Low-Density Parity-Check (LDPC) codes using sparse binary sequences. It utilizes the cyclic cross correlation function of sparse sequences to generate co...This letter proposes a novel and simple construction of regular Low-Density Parity-Check (LDPC) codes using sparse binary sequences. It utilizes the cyclic cross correlation function of sparse sequences to generate codes with girth8. The new codes perform well using the sumproduct decoding. Low encodingcomplexity can also be achieved due to the inherent quasi-cyclic structure of the codes.展开更多
时延是现代通信系统的一个重要指标。滑动窗译码能够在保证性能的基础上降低时延。基于滑动窗译码提出了一种不规则原模图低密度奇偶校验(low density parity check,LDPC)卷积码的构造方法。通过对基于AR4JA(accumulate-repeat-by-4-jag...时延是现代通信系统的一个重要指标。滑动窗译码能够在保证性能的基础上降低时延。基于滑动窗译码提出了一种不规则原模图低密度奇偶校验(low density parity check,LDPC)卷积码的构造方法。通过对基于AR4JA(accumulate-repeat-by-4-jagged-accumulate)的LDPC卷积码在AWGN(additive white Gaussian noise)信道下的P-EXIT性能分析发现,利用这种构造方式能够设计出多码率并且在BP译码和滑动窗译码方式下都能逼近容量限的LDPC卷积码。计算机仿真证明了基于AR4JA的LDPC卷积码性能优于规则的LDPC卷积码,而且在滑动窗译码方式下在降低至少56.7%时延的同时表现出了很好的性能。结合提出的不规则原模图LDPC卷积码的构造方法和滑动窗译码得到了一种能够实现译码时延与码字性能良好折中的码字构造有效方式。展开更多
基金supported by the National Natural Science Foundation of China(No.91538203)the new strategic industries development projects of Shenzhen City(No.JCYJ20150403155812833)
文摘When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
基金supported in part by the National Natural Science Foundation of China (Nos. 61101072 and 61132002)the new strategic industries development projects of Shenzhen city (No. ZDSY20120616141333842)Tsinghua University Initiative Scientific Research Program (No. 2012Z10132)
文摘The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.
基金the National Natural Science Foundation of China(Nos.61401164,61471131 and 61201145)the Natural Science Foundation of Guangdong Province(No.2014A030310308)
文摘In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are derived by permuting the matrices of the corresponding RC-LDPC block codes,are systematic and have maximum encoding memory.Simulation results show that the proposed RC-LDPC convolutional codes with belief propagation(BP) decoding collectively offer a steady improvement on performance compared with the block counterparts over the binary-input additive white Gaussian noise channels(BI-AWGNCs).
基金supported by the National Basic Research Project of China(973)(2013CB329006)National Natural Science Foundation of China(NSFC,91538203)the new strategic industries development projects of Shenzhen City(JCYJ20150403155812833)
文摘Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.
基金Supported by the National Key Basic Research and Development (973) Program of China (No.2009CB320300)
文摘The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for decoding LDPC codes that includes a slight increase in computational complexity.The MLP decoder adaptively adds new constraints which are compatible with a selected check node to refine the results when an error is reported by the original LP decoder.The MLP decoder result is shown to have the maximum-likelihood（ML） certificate property.Simulations with moderate block length LDPC codes suggest that the MLP decoder gives better performance than both the original LP decoder and the conventional sum-product（SP） decoder.
基金The National High Technology Research and Development Program of China (863Program) ( No2009AA01Z235,2006AA01Z263)the Research Fund of the National Mobile Communications Research Laboratory of Southeast University(No2008A10)
文摘An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.
基金the National Key Research and Development Program of China under Grant No.2018YF-A0701800the National Natural Science Foundation of China under Grant Nos.61821003 and 62172175,and Alibaba Group through Alibaba Innovative Research(AIR)Program.
文摘Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.
基金Supported by Key Project of the National Natural Science Foundation of China (No.60496311).
文摘This letter proposes a novel and simple construction of regular Low-Density Parity-Check (LDPC) codes using sparse binary sequences. It utilizes the cyclic cross correlation function of sparse sequences to generate codes with girth8. The new codes perform well using the sumproduct decoding. Low encodingcomplexity can also be achieved due to the inherent quasi-cyclic structure of the codes.
基金The National Natural Science Foundation of China(61271241)~~
文摘时延是现代通信系统的一个重要指标。滑动窗译码能够在保证性能的基础上降低时延。基于滑动窗译码提出了一种不规则原模图低密度奇偶校验(low density parity check,LDPC)卷积码的构造方法。通过对基于AR4JA(accumulate-repeat-by-4-jagged-accumulate)的LDPC卷积码在AWGN(additive white Gaussian noise)信道下的P-EXIT性能分析发现,利用这种构造方式能够设计出多码率并且在BP译码和滑动窗译码方式下都能逼近容量限的LDPC卷积码。计算机仿真证明了基于AR4JA的LDPC卷积码性能优于规则的LDPC卷积码,而且在滑动窗译码方式下在降低至少56.7%时延的同时表现出了很好的性能。结合提出的不规则原模图LDPC卷积码的构造方法和滑动窗译码得到了一种能够实现译码时延与码字性能良好折中的码字构造有效方式。
