本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度....本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度.电路在0.5μm VIS CMOS工艺下实现,温度系数29×10-6V/℃,20mV输入失调电压下的电压漂移仅为0.4mV.展开更多
高失调电压和低磁场灵敏度严重影响了CMOS集成2D垂直型霍尔传感器的应用。提出了一种新颖的2D垂直型霍尔传感器失调消除和信号放大电路。采用2相旋转电流调制和相关双采样解调技术实现了对霍尔失调有效消除;采用信号复用技术实现了对X轴...高失调电压和低磁场灵敏度严重影响了CMOS集成2D垂直型霍尔传感器的应用。提出了一种新颖的2D垂直型霍尔传感器失调消除和信号放大电路。采用2相旋转电流调制和相关双采样解调技术实现了对霍尔失调有效消除;采用信号复用技术实现了对X轴和Y轴输入的2D霍尔信号进行相同处理,避免了2轴霍尔信号之间的放大误差,大大降低了电路的功耗。基于CSMC 0.8μm高压CMOS工艺进行了电路设计,仿真结果表明该电路能最大消除40 m V霍尔失调电压,并对最小0.4 m V的2轴霍尔信号放大并线性输出霍尔电压。输出霍尔电压的线性度大于99.9%,电路静态功耗小于20 m W。展开更多
An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap r...An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap reference with limited loop bandwidth and slow start-up feature, to generate a reset signal with high robustness and wide-range supply rise time. An embedded brown- out detector based on complementary voltage-to-current （V-to-I） conversion and current comparison can accurately respond to the brown-out event with high robustness over process and temperature when the supply is lower than 1.5 V and the brown-out duration is longer than 0. 1 ms. The presented design with embedded offset voltage cancellation consumes a quiescent current of 8. 5 μA from a 1. 8 V supply and works over ambient temperature of -40° to 120°.展开更多
This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpo...This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.展开更多
文摘本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度.电路在0.5μm VIS CMOS工艺下实现,温度系数29×10-6V/℃,20mV输入失调电压下的电压漂移仅为0.4mV.
文摘高失调电压和低磁场灵敏度严重影响了CMOS集成2D垂直型霍尔传感器的应用。提出了一种新颖的2D垂直型霍尔传感器失调消除和信号放大电路。采用2相旋转电流调制和相关双采样解调技术实现了对霍尔失调有效消除;采用信号复用技术实现了对X轴和Y轴输入的2D霍尔信号进行相同处理,避免了2轴霍尔信号之间的放大误差,大大降低了电路的功耗。基于CSMC 0.8μm高压CMOS工艺进行了电路设计,仿真结果表明该电路能最大消除40 m V霍尔失调电压,并对最小0.4 m V的2轴霍尔信号放大并线性输出霍尔电压。输出霍尔电压的线性度大于99.9%,电路静态功耗小于20 m W。
基金Supported by the National Natural Science Foundation of China(6130603761201182)
文摘An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap reference with limited loop bandwidth and slow start-up feature, to generate a reset signal with high robustness and wide-range supply rise time. An embedded brown- out detector based on complementary voltage-to-current （V-to-I） conversion and current comparison can accurately respond to the brown-out event with high robustness over process and temperature when the supply is lower than 1.5 V and the brown-out duration is longer than 0. 1 ms. The presented design with embedded offset voltage cancellation consumes a quiescent current of 8. 5 μA from a 1. 8 V supply and works over ambient temperature of -40° to 120°.
基金supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028)the National High-Tech Research and Development Program of China(No.2009AA01Z258)the National Science & Technology Important Project of China (No.2009ZX01034-002001-005)
文摘This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.
