A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity...A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.展开更多
This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and ...This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.展开更多
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.展开更多
This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirem...This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirement between the first multiplying digital-to-analog converter（MDAC） and sub-ADC is also avoided by using the SHA merged with the first MDAC（SMDAC） architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages,in which the effect of opamp offset and crosstalk between stages is decreased.So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB,respectively,with a Nyquist input at full sampling rate.Constant dynamic performance for input frequencies up to 49.7 MHz,which is the twofold Nyquist rate,is achieved at 50 MS/s.The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35μm CMOS process,and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.
文摘This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.
基金Project supported by the National Natural Science Foundation of China(No.60876019)the National S&T Major Project of China(No. 2009ZX0131-002-003-02)+2 种基金the Shanghai Rising-Star Program(No.09QA1400300)the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046)the ASIC State-Key Laboratory Funding,China(No.09MS007)
文摘A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
文摘This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirement between the first multiplying digital-to-analog converter（MDAC） and sub-ADC is also avoided by using the SHA merged with the first MDAC（SMDAC） architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages,in which the effect of opamp offset and crosstalk between stages is decreased.So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB,respectively,with a Nyquist input at full sampling rate.Constant dynamic performance for input frequencies up to 49.7 MHz,which is the twofold Nyquist rate,is achieved at 50 MS/s.The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35μm CMOS process,and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.
