Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encr...Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encrypted images,we proposed a reversible data hiding algorithm for encrypted images based on prediction and adaptive classification scrambling.First,the prediction error image is obtained by a novel prediction method before encryption.Then,the image pixel values are divided into two categories by the threshold range,which is selected adaptively according to the image content.Multiple high-significant bits of pixels within the threshold range are used for embedding data and pixel values outside the threshold range remain unchanged.The optimal threshold selected adaptively ensures the maximum embedding capacity of the algorithm.Moreover,the security of encrypted images can be improved by the combination of XOR encryption and classification scrambling encryption since the embedded data is independent of the pixel position.Experiment results demonstrate that the proposed method has higher embedding capacity compared with the current state-of-the-art methods for images with different texture complexity.展开更多
Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit seq...Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.展开更多
In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurre...In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurrence histogram for each B × B sub-block can be utilized to describe the texture of the image. Moreover, using a new multi-bit plane strategy, i.e., representing the image texture with the occurrence histogram of the first one or more significant bit-planes of the input image, more powerful operators for describing the image texture can be obtained. The proposed approach is invariant to gray scale variations since the operators are, by definition,invariant under any monotonic transformation of the gray scale, and robust to rotation. They can also be used as supplementary operators to local binary patterns(LBP) to improve their capability to resist illuminance variation, surface transformations, etc.展开更多
A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded ...A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of t...This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.展开更多
A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower cl...A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average（DWA） mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range（DR） and peak SNDR are 96 dB and 88 dB,respectively.展开更多
For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the r...For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.展开更多
基金supported by the National Natural Science Foundation of China(61872303,U1936113)the Science and Technology Innovation Talents Program of Sichuan Science and Technology Department(2018RZ0143)the Key Project of Sichuan Science and Technology Innovation Pioneering Miaozi Project(19MZGC0163).
文摘Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encrypted images,we proposed a reversible data hiding algorithm for encrypted images based on prediction and adaptive classification scrambling.First,the prediction error image is obtained by a novel prediction method before encryption.Then,the image pixel values are divided into two categories by the threshold range,which is selected adaptively according to the image content.Multiple high-significant bits of pixels within the threshold range are used for embedding data and pixel values outside the threshold range remain unchanged.The optimal threshold selected adaptively ensures the maximum embedding capacity of the algorithm.Moreover,the security of encrypted images can be improved by the combination of XOR encryption and classification scrambling encryption since the embedded data is independent of the pixel position.Experiment results demonstrate that the proposed method has higher embedding capacity compared with the current state-of-the-art methods for images with different texture complexity.
基金Supported by the National Natural Science Foundation of China (No.60172029) and the Natural Science Foun-dation of Shaanxi Province (No.2004F04).
文摘Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.
基金partially supported by the National Natural Science Foundation of China (61173147, 61332012, and U1135001)the National Basic Research Program of China (2011CB302204)+2 种基金the Fundamental Research Funds for Central Universities (12lgpy31)the Korea Foundation for Advanced Studies’ International Scholar Exchange Fellowship for the academic year of 2013–2014the MKE (The Ministry of Knowledge Economy), R. O. Korea, under the ITRC support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2010-C1090-1001-0004)
文摘In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurrence histogram for each B × B sub-block can be utilized to describe the texture of the image. Moreover, using a new multi-bit plane strategy, i.e., representing the image texture with the occurrence histogram of the first one or more significant bit-planes of the input image, more powerful operators for describing the image texture can be obtained. The proposed approach is invariant to gray scale variations since the operators are, by definition,invariant under any monotonic transformation of the gray scale, and robust to rotation. They can also be used as supplementary operators to local binary patterns(LBP) to improve their capability to resist illuminance variation, surface transformations, etc.
文摘A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
基金supported by the National High Technology Research and Development Program of China(No.2008AA010700).
文摘This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.
文摘A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average（DWA） mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range（DR） and peak SNDR are 96 dB and 88 dB,respectively.
文摘For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.
