Photonics-based radar with a photonic de-chirp receiver has the advantages of broadband operation and real-time signal processing, but it suffers from interference from image frequencies and other undesired frequency-...Photonics-based radar with a photonic de-chirp receiver has the advantages of broadband operation and real-time signal processing, but it suffers from interference from image frequencies and other undesired frequency-mixing components, due to single-channel real-valued photonic frequency mixing. In this paper, we propose a photonicsbased radar with a photonic frequency-doubling transmitter and a balanced in-phase and quadrature(I/Q)de-chirp receiver. This radar transmits broadband linearly frequency-modulated signals generated by photonic frequency doubling and performs I/Q de-chirping of the radar echoes based on a balanced photonic I/Q frequency mixer, which is realized by applying a 90° optical hybrid followed by balanced photodetectors. The proposed radar has a high range resolution because of the large operation bandwidth and achieves interference-free detection by suppressing the image frequencies and other undesired frequency-mixing components. In the experiment, a photonics-based K-band radar with a bandwidth of 8 GHz is demonstrated. The balanced I/Q de-chirping receiver achieves an image-rejection ratio of over 30 dB and successfully eliminates the interference due to the baseband envelope and the frequency mixing between radar echoes of different targets. In addition, the desired dechirped signal power is also enhanced with balanced detection. Based on the established photonics-based radar,inverse synthetic aperture radar imaging is also implemented, through which the advantages of the proposed radar are verified.展开更多
The mismatch of ill-phase and quadrature channels in quadrature receiver affects and constrains radar detection performance in coherent radar. It is necessary to keep the in-phase and quadrature branches symmetrical. ...The mismatch of ill-phase and quadrature channels in quadrature receiver affects and constrains radar detection performance in coherent radar. It is necessary to keep the in-phase and quadrature branches symmetrical. In this letter, an adaptive method t.o detect imbalance parameters is derived by means of evaluating channel errors from the received signal .sequences. No matter how the bias degree of the gain and phase errors in I/Q channels are. the proposed adaptive scheme can obtain good calibration results. And the inquired calculations are only a few multiplications and additions. No need of a special test signal, the introduced method is simple to implement and easy to operate.展开更多
A down-conversion in-phase/quadrature (l/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of...A down-conversion in-phase/quadrature (l/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider tbr the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP3) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.展开更多
A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detecto...A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could altematively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μs with 80% AM input with measured signal power from -76.7 to -56.6 dBm from a radio-frequency amplifier (RFA) input port, and also reduces to 90 #s with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.展开更多
A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only ...A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only needs a calibration chain to detect mismatches and then transmit them to the digital baseband.Simulation results show that the calibrated errors of the proposed technique are less than 7%.The measurement results indicate the function of the proposed technique is correct,but the performance should be improved further.展开更多
Optimization of mapping rule of bit-interleaved Turbo coded modulation with 16 quadrature amplitude modulation (QAM) is investigated based on different impacts of various encoded bits sequence on Turbo decoding perfor...Optimization of mapping rule of bit-interleaved Turbo coded modulation with 16 quadrature amplitude modulation (QAM) is investigated based on different impacts of various encoded bits sequence on Turbo decoding performance. Furthermore, bit-interleaved in-phase and quadrature phase (I-Q) Turbo coded modulation scheme are designed similarly with I-Q trellis coded modulation (TCM). Through performance evaluation and analysis, it can be seen that the novel mapping rule outperforms traditional one and the I-Q Turbo coded modulation can not achieve good performance as expected. Therefore, there is not obvious advantage in using I-Q method in bit-interleaved Turbo coded modulation.展开更多
Radio frequency (RF) front-end nonidealities in multi-input and multi-output (MIMO) systems are more serious than in single-input and single-output systems and must be calibrated. According to the effects of RF po...Radio frequency (RF) front-end nonidealities in multi-input and multi-output (MIMO) systems are more serious than in single-input and single-output systems and must be calibrated. According to the effects of RF power and in-phase/quadrature-phase (I/Q) imbalance, calibration methods for multi-input and multi-output-orthogonal frequency division multiplexing (MIMC-OFDM) systems in transmitter and interference in receiver are improved, respectively, in this article Furthermore, a calibration scheme including I/Q imbalance errors and amplitude variations is proposed and implemented in the B3G/4G time division duplex communication system. Simulation results show that the calibration algorithms are feasible, and the bit error rate (BER) performances for MIMO-OFDM systems are improved after calibrations.展开更多
A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip ...A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.展开更多
Since Global Navigation Satellite System(GNSS) signals span a wide range of frequency, wireless signals coming from other communication systems may be aliased and appear as image interference. In quadrature intermed...Since Global Navigation Satellite System(GNSS) signals span a wide range of frequency, wireless signals coming from other communication systems may be aliased and appear as image interference. In quadrature intermediate frequency(IF) receivers, image aliasing due to in-phase and quadrature(I/Q) channel mismatches is always a big problem. I/Q mismatches occur because of gain and phase imbalances between quadrature mixers and capacitor mismatches in analog-to-digital converters(ADC). As a result, the dynamic range and performance of a receiver are severely degraded. In this paper, several popular receiver architectures are summarized and the image aliasing problem is investigated in detail. Based on this analysis, a low-IF architecture is proposed for a single-chip solution and a novel and feasible anti-image algorithm is investigated. With this anti-image digital processing, the image reject ratio(IRR) can reach approximately above50 dB, which relaxes image rejection specific in front-end circuit designs and allows cheap and highly flexible analog front-end solutions. Simulation and experimental data show that the antiimage algorithm can work effectively, robustly, and steadily.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
基金National Natural Science Foundation of China(NSFC)(61871214,61527820)Natural Science Foundation of Jiangsu Province(BK20180066)+1 种基金The Jiangsu Provincial Program for High-level Talents in Six Areas(DZXX-005)Fundamental Research Funds for the Central Universities(NS2018028,NC2018005)
文摘Photonics-based radar with a photonic de-chirp receiver has the advantages of broadband operation and real-time signal processing, but it suffers from interference from image frequencies and other undesired frequency-mixing components, due to single-channel real-valued photonic frequency mixing. In this paper, we propose a photonicsbased radar with a photonic frequency-doubling transmitter and a balanced in-phase and quadrature(I/Q)de-chirp receiver. This radar transmits broadband linearly frequency-modulated signals generated by photonic frequency doubling and performs I/Q de-chirping of the radar echoes based on a balanced photonic I/Q frequency mixer, which is realized by applying a 90° optical hybrid followed by balanced photodetectors. The proposed radar has a high range resolution because of the large operation bandwidth and achieves interference-free detection by suppressing the image frequencies and other undesired frequency-mixing components. In the experiment, a photonics-based K-band radar with a bandwidth of 8 GHz is demonstrated. The balanced I/Q de-chirping receiver achieves an image-rejection ratio of over 30 dB and successfully eliminates the interference due to the baseband envelope and the frequency mixing between radar echoes of different targets. In addition, the desired dechirped signal power is also enhanced with balanced detection. Based on the established photonics-based radar,inverse synthetic aperture radar imaging is also implemented, through which the advantages of the proposed radar are verified.
文摘The mismatch of ill-phase and quadrature channels in quadrature receiver affects and constrains radar detection performance in coherent radar. It is necessary to keep the in-phase and quadrature branches symmetrical. In this letter, an adaptive method t.o detect imbalance parameters is derived by means of evaluating channel errors from the received signal .sequences. No matter how the bias degree of the gain and phase errors in I/Q channels are. the proposed adaptive scheme can obtain good calibration results. And the inquired calculations are only a few multiplications and additions. No need of a special test signal, the introduced method is simple to implement and easy to operate.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010200)
文摘A down-conversion in-phase/quadrature (l/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider tbr the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP3) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.
基金supported by the National Natural Science Foundation of China(Nos.60806008,61076029)the National High Technology Research and Development Program of China(No.2009AA011606)the National Science and Technology Major Projects of China(No. 2009ZX03007-001)
文摘A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could altematively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μs with 80% AM input with measured signal power from -76.7 to -56.6 dBm from a radio-frequency amplifier (RFA) input port, and also reduces to 90 #s with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.
基金Project supported by the Doctoral Scientific Starting Research from the Xi'an Polytechnic University(No.BS1209)the Shaanxi Provincial Education Department(No.12JK0546)
文摘A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only needs a calibration chain to detect mismatches and then transmit them to the digital baseband.Simulation results show that the calibrated errors of the proposed technique are less than 7%.The measurement results indicate the function of the proposed technique is correct,but the performance should be improved further.
文摘Optimization of mapping rule of bit-interleaved Turbo coded modulation with 16 quadrature amplitude modulation (QAM) is investigated based on different impacts of various encoded bits sequence on Turbo decoding performance. Furthermore, bit-interleaved in-phase and quadrature phase (I-Q) Turbo coded modulation scheme are designed similarly with I-Q trellis coded modulation (TCM). Through performance evaluation and analysis, it can be seen that the novel mapping rule outperforms traditional one and the I-Q Turbo coded modulation can not achieve good performance as expected. Therefore, there is not obvious advantage in using I-Q method in bit-interleaved Turbo coded modulation.
文摘Radio frequency (RF) front-end nonidealities in multi-input and multi-output (MIMO) systems are more serious than in single-input and single-output systems and must be calibrated. According to the effects of RF power and in-phase/quadrature-phase (I/Q) imbalance, calibration methods for multi-input and multi-output-orthogonal frequency division multiplexing (MIMC-OFDM) systems in transmitter and interference in receiver are improved, respectively, in this article Furthermore, a calibration scheme including I/Q imbalance errors and amplitude variations is proposed and implemented in the B3G/4G time division duplex communication system. Simulation results show that the calibration algorithms are feasible, and the bit error rate (BER) performances for MIMO-OFDM systems are improved after calibrations.
文摘A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.
基金co-supported by Western Light Talent Culture Project of China(No.2013BS25)the National Natural Science Foundation of China(No.11203027)
文摘Since Global Navigation Satellite System(GNSS) signals span a wide range of frequency, wireless signals coming from other communication systems may be aliased and appear as image interference. In quadrature intermediate frequency(IF) receivers, image aliasing due to in-phase and quadrature(I/Q) channel mismatches is always a big problem. I/Q mismatches occur because of gain and phase imbalances between quadrature mixers and capacitor mismatches in analog-to-digital converters(ADC). As a result, the dynamic range and performance of a receiver are severely degraded. In this paper, several popular receiver architectures are summarized and the image aliasing problem is investigated in detail. Based on this analysis, a low-IF architecture is proposed for a single-chip solution and a novel and feasible anti-image algorithm is investigated. With this anti-image digital processing, the image reject ratio(IRR) can reach approximately above50 dB, which relaxes image rejection specific in front-end circuit designs and allows cheap and highly flexible analog front-end solutions. Simulation and experimental data show that the antiimage algorithm can work effectively, robustly, and steadily.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.