We present a 10 Gsps 8 bit digital-to-analog converter （DAC） with a novel built-in self-test （BIST） circuit, which makes it possible to evaluate the DAC＇s performance without a complicated test setup. Design con-...We present a 10 Gsps 8 bit digital-to-analog converter （DAC） with a novel built-in self-test （BIST） circuit, which makes it possible to evaluate the DAC＇s performance without a complicated test setup. Design con- siderations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260 × 250μm^2.展开更多
基金Project supported by the State Key Development Program for Basic Research of China(No.2010CB327505)
文摘We present a 10 Gsps 8 bit digital-to-analog converter （DAC） with a novel built-in self-test （BIST） circuit, which makes it possible to evaluate the DAC＇s performance without a complicated test setup. Design con- siderations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260 × 250μm^2.
文摘设计并实现了应用于2.8 G高速DAC芯片的内部测试电路,该电路输出两路线性斜坡信号作为DAC模块的输入数据,DAC模块将其合成为一路线性斜坡信号输出。通过设计实验和多种设计方案优缺点比较,该测试电路最终采用两路并行累加器架构,克服了传统累加器结构无法用于高速电路的固有缺陷。在65 nm工艺下,基于此测试电路设计了测试芯片并进行了流片验证。测试结果表明:测试芯片整体可达到2.8 G SPS的测试速度,实现了对吉赫兹DAC全扫描测试的设计目标。
