The paper presents the simulation results of the comparison of three Queuing Mechanisms, First in First out (FIFO), Priority Queuing (PQ), and Weighted Fair Queuing (WFQ). Depending on their effects on the network’s ...The paper presents the simulation results of the comparison of three Queuing Mechanisms, First in First out (FIFO), Priority Queuing (PQ), and Weighted Fair Queuing (WFQ). Depending on their effects on the network’s Routers, the load of any algorithm of them over Router’s CPUs and memory usage, the delay occurred between routers when any algorithm has been used and the network application throughput. This comparison explains that, PQ doesn’t need high specification hardware (memory and CPU) but when used it is not fair, because it serves one application and ignore the other application and FIFO mechanism has smaller queuing delay, otherwise PQ has bigger delay.展开更多
文摘The paper presents the simulation results of the comparison of three Queuing Mechanisms, First in First out (FIFO), Priority Queuing (PQ), and Weighted Fair Queuing (WFQ). Depending on their effects on the network’s Routers, the load of any algorithm of them over Router’s CPUs and memory usage, the delay occurred between routers when any algorithm has been used and the network application throughput. This comparison explains that, PQ doesn’t need high specification hardware (memory and CPU) but when used it is not fair, because it serves one application and ignore the other application and FIFO mechanism has smaller queuing delay, otherwise PQ has bigger delay.
文摘为满足现代高分辨率雷达大容量高速缓存以及被动雷达和时差定位系统采样预触发的需要,提出了采用多片先进先出(F IFO)芯片级联的硬件结构实现可编程采样预触发和缓存容量扩展.分析了两级F IFO级联时芯片间接口的时序,给出了对F IFO可编程标志位的设置方法.实际应用证明,采用该结构可使系统的缓存容量达到2 M B,预触发量达到1 M B,且两种功能可由FPGA控制切换.该结构也适用于其它具有可编程标志的F IFO.
