准确建立风电机组模型是研究其动态物理过程及运行特性的基础。现有部分电力系统商业软件模型库中缺失永磁同步电机模型,给直驱永磁风电机组模型的建立带来困难。为解决这一问题,提出一种采用电励磁同步电机等效永磁同步电机的方法,给...准确建立风电机组模型是研究其动态物理过程及运行特性的基础。现有部分电力系统商业软件模型库中缺失永磁同步电机模型,给直驱永磁风电机组模型的建立带来困难。为解决这一问题,提出一种采用电励磁同步电机等效永磁同步电机的方法,给出这两种电机参数转换公式;在此基础上,以DIg SILENT Power Factory为例,采用电励磁同步电机代替永磁同步电机,对直驱风电机组模型进行实现,提炼建模过程中的关键点与注意事项。仿真结果表明,采用发电机等效方法建立的直驱风电机组各模块的输出对于扰动响应有效合理,且在风速扰动和三相短路故障条件下,提供给电励磁同步电机以维持恒定转子磁场的励磁电流均能快速有效跟踪其初始给定值。展开更多
This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized ...This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.展开更多
文摘准确建立风电机组模型是研究其动态物理过程及运行特性的基础。现有部分电力系统商业软件模型库中缺失永磁同步电机模型,给直驱永磁风电机组模型的建立带来困难。为解决这一问题,提出一种采用电励磁同步电机等效永磁同步电机的方法,给出这两种电机参数转换公式;在此基础上,以DIg SILENT Power Factory为例,采用电励磁同步电机代替永磁同步电机,对直驱风电机组模型进行实现,提炼建模过程中的关键点与注意事项。仿真结果表明,采用发电机等效方法建立的直驱风电机组各模块的输出对于扰动响应有效合理,且在风速扰动和三相短路故障条件下,提供给电励磁同步电机以维持恒定转子磁场的励磁电流均能快速有效跟踪其初始给定值。
基金Honeywell Process SolutionsUSA合作研究项目基金+5 种基金国家"863"高技术研究发展计划基金(No.2009AA01Z212No.200901Z202)江苏省自然科学基金(No.BK2007603)江苏省高技术研究计划基金(No.BG2007045)南京信息工程大学校科研基金(No.20070025)南京邮电大学攀登计划基金(No.NY2007044)资助
文摘This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.
