The major drawback in Orthogonal Frequency Division Multiplexing (OFDM) system is due to the high Peak-to-Average Power Ratio (PAPR), so the performance of the system is significantly degraded by the nonlinearity of a...The major drawback in Orthogonal Frequency Division Multiplexing (OFDM) system is due to the high Peak-to-Average Power Ratio (PAPR), so the performance of the system is significantly degraded by the nonlinearity of a High Power Amplifier (HPA) in the transmitter.In order to mitigate distortion, a block coding scheme for reducing PAPR in OFDM systems with large number of subcarriers based on complementary sequences and predistortion is proposed,which is capable of both error correction and PAPR reduction. Computer simulation results show that the proposed scheme significantly improves Bit Error Rate(BER) performance as compared to an uncoded system when an HPA is employed or a coded system without predistortion.展开更多
The depletion of fossil energy and the deterioration of the ecological environment have severely restricted the development of the power industry.Therefore,it is extremely urgent to transform energy production methods...The depletion of fossil energy and the deterioration of the ecological environment have severely restricted the development of the power industry.Therefore,it is extremely urgent to transform energy production methods and vigorously develop renewable energy sources.It is therefore important to ensure the stability and operation of a large multi-energy complementary system,and provide theoretical support for the world’s largest single complementary demonstration project with hydro-wind-PV power-battery storage in Qinghai Province.Considering all the multiple power supply constraints,an optimization scheduling model is established with the objective of minimizing the volatility of output power.As particle swarm optimization(PSO)has a problem of premature convergence and slow convergence in the latter half,combined with niche technology in evolution,a niche particle swarm optimization(NPSO)is proposed to determine the optimal solution of the model.Finally,the multiple stations’coordinated operation is analyzed taking the example of 10 million kilowatt complementary power stations with hydropower,wind power,PV power,and battery storage in the Yellow River Company Hainan prefecture.The case verifies the rationality and feasibility of the model.It shows that complementary operations can improve the utilization rate of renewable energy and reduce the impact of wind and PV power’s volatility on the power grid.展开更多
To improve the operation efficiency of the photovoltaic power station complementary power generation system,an optimal allocation model of the photovoltaic power station complementary power generation capacity based o...To improve the operation efficiency of the photovoltaic power station complementary power generation system,an optimal allocation model of the photovoltaic power station complementary power generation capacity based on PSO-BP is proposed.Particle Swarm Optimization and BP neural network are used to establish the forecasting model,the Markov chain model is used to correct the forecasting error of the model,and the weighted fitting method is used to forecast the annual load curve,to complete the optimal allocation of complementary generating capacity of photovoltaic power stations.The experimental results show that thismethod reduces the average loss of photovoltaic output prediction,improves the prediction accuracy and recall rate of photovoltaic output prediction,and ensures the effective operation of the power system.展开更多
A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM...A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FET...Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.展开更多
This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The...This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best PIdB is -7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 ×0.2 mm2.展开更多
A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplific...A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
基金Supported in part by the National 863 program of China(No.2001AA123014)
文摘The major drawback in Orthogonal Frequency Division Multiplexing (OFDM) system is due to the high Peak-to-Average Power Ratio (PAPR), so the performance of the system is significantly degraded by the nonlinearity of a High Power Amplifier (HPA) in the transmitter.In order to mitigate distortion, a block coding scheme for reducing PAPR in OFDM systems with large number of subcarriers based on complementary sequences and predistortion is proposed,which is capable of both error correction and PAPR reduction. Computer simulation results show that the proposed scheme significantly improves Bit Error Rate(BER) performance as compared to an uncoded system when an HPA is employed or a coded system without predistortion.
文摘The depletion of fossil energy and the deterioration of the ecological environment have severely restricted the development of the power industry.Therefore,it is extremely urgent to transform energy production methods and vigorously develop renewable energy sources.It is therefore important to ensure the stability and operation of a large multi-energy complementary system,and provide theoretical support for the world’s largest single complementary demonstration project with hydro-wind-PV power-battery storage in Qinghai Province.Considering all the multiple power supply constraints,an optimization scheduling model is established with the objective of minimizing the volatility of output power.As particle swarm optimization(PSO)has a problem of premature convergence and slow convergence in the latter half,combined with niche technology in evolution,a niche particle swarm optimization(NPSO)is proposed to determine the optimal solution of the model.Finally,the multiple stations’coordinated operation is analyzed taking the example of 10 million kilowatt complementary power stations with hydropower,wind power,PV power,and battery storage in the Yellow River Company Hainan prefecture.The case verifies the rationality and feasibility of the model.It shows that complementary operations can improve the utilization rate of renewable energy and reduce the impact of wind and PV power’s volatility on the power grid.
文摘To improve the operation efficiency of the photovoltaic power station complementary power generation system,an optimal allocation model of the photovoltaic power station complementary power generation capacity based on PSO-BP is proposed.Particle Swarm Optimization and BP neural network are used to establish the forecasting model,the Markov chain model is used to correct the forecasting error of the model,and the weighted fitting method is used to forecast the annual load curve,to complete the optimal allocation of complementary generating capacity of photovoltaic power stations.The experimental results show that thismethod reduces the average loss of photovoltaic output prediction,improves the prediction accuracy and recall rate of photovoltaic output prediction,and ensures the effective operation of the power system.
基金The National Natural Science Foundation of China(No. 61106024)the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20090092120012)the Science and Technology Program of South east University (No. KJ2010402)
文摘A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金supported in part by the Hong Kong Research Impact Fund(Grant No.R6008-18)the Shen-zhen Science and Technology Innovation Commission(Grant No.SGDX2020110309460101).
文摘Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.
基金Project supported by the Ministry of Industry and Information Technology,China(No.2009ZX03006-009)
文摘This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best PIdB is -7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 ×0.2 mm2.
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
