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Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale
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作者 Mohammad Hossein Moaiyeri Ali Jahanian Keivan Navi 《Nano-Micro Letters》 SCIE EI CAS 2011年第3期178-188,共11页
Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have c... Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller. 展开更多
关键词 carbon nanotube field effect transistor(cnfet) FPGA switches Performance evaluation Power consumption Process variation
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基于CNFET的高性能三值SRAM-PUF电路设计
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作者 汪鹏君 龚道辉 +1 位作者 张会红 康耀鹏 《电子学报》 EI CAS CSCD 北大核心 2017年第5期1090-1095,共6页
通过对碳纳米管场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和物理不可克隆函(Physical Unclonable Functions,PUF)电路的研究,提出一种高性能三值SRAM-PUF电路结构.该电路结构首先利用交叉耦合三值反相器产生随机电... 通过对碳纳米管场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和物理不可克隆函(Physical Unclonable Functions,PUF)电路的研究,提出一种高性能三值SRAM-PUF电路结构.该电路结构首先利用交叉耦合三值反相器产生随机电流,并对其电流进行失配分析;然后结合三值SRAM单元的电流竞争得到随机的、不可克隆的三值输出信号"0"、"1"和"2".在32nm CNFET标准模型库下,采用HSPICE对所设计的三值SRAM-PUF电路进行Monte Carlo仿真,分析其随机性、唯一性等性能.模拟结果表明所设计的三值SRAM-PUF电路归一化随机性偏差和唯一性偏差均为0.03%,且与传统二值CMOS设计的PUF电路相比工作速度提高33%,激励响应对数量为原来的(1.5)n倍. 展开更多
关键词 碳纳米管场效应晶体管 三值逻辑 SRAM-PUF 随机性 唯一性
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