Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technol...Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.展开更多
To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and intern...To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.展开更多
基金supported by the Harbin Science and Innovation Research.(Grant No.2012RFXXG042)
文摘Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.
文摘To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.
