本文以Xilinx公司基于SRAM的FPGA XC4010为研究对象,将FP- GA配置成两种电路来完成对可编程逻辑模块(CLB)的测试,并阐述了如何在Teradyne商用ATE(Automatic Test Equipment)J750上实现FPGA的在线配置及测试,为FPGA面向应用的测试提供一...本文以Xilinx公司基于SRAM的FPGA XC4010为研究对象,将FP- GA配置成两种电路来完成对可编程逻辑模块(CLB)的测试,并阐述了如何在Teradyne商用ATE(Automatic Test Equipment)J750上实现FPGA的在线配置及测试,为FPGA面向应用的测试提供一种有效的方法。展开更多
FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other typ...FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.展开更多
Objective To investigate effects of clenbuterol （CLB） on testicular ultrastructure of rat. Methods Twenty adult male Sprague-Dawley rats were randomly divided into four groups （5 rats per group）. CLB solved in nor...Objective To investigate effects of clenbuterol （CLB） on testicular ultrastructure of rat. Methods Twenty adult male Sprague-Dawley rats were randomly divided into four groups （5 rats per group）. CLB solved in normal saline solution was given at the dose of O mg/kg body weight （bw） （group A, as control）, 0.4 mg/kg bw （group B）, 2.0 mg/kg bw （group C）, and 18.5 mg/kg bw （group D）for 14 d by garage consecutively, respectively. Transmission electron microscopy was used to observe changes on testicular ultrastructure. Results In group B, some small vacuoles were found in Sertoli cells. In groups C and D, vacuoles were common in Sertoli cells and spermatogonia. The phenomenon of vacuolation in group D was more severe than that in group C. In group D, basal membrane showed some irregular and wrinkled changes, Leydig cells had more vacuoles and increased lipid droplets. Conclusion Testicular ultrastructure of rat had pathological changes after CLB exposure, and the alterations became more severe with the increasing doses.展开更多
Interconnected cells,Configurable Logic Blocks(CLBs),and input/output(I/O)pads are all present in every Field Programmable Gate Array(FPGA)structure.The interconnects are formed by the physical paths for connecting th...Interconnected cells,Configurable Logic Blocks(CLBs),and input/output(I/O)pads are all present in every Field Programmable Gate Array(FPGA)structure.The interconnects are formed by the physical paths for connecting the blocks.The combinational and sequential circuits are used in the logic blocks to execute logical functions.The FPGA includes two different tests called interconnect testing and logical testing.Instead of using an additional circuitry,the Built-in-Self-Test(BIST)logic is coded into an FPGA,which is then reconfigured to perform its specific operation after the testing is completed.As a result,additional test circuits for the FPGA board are no longer required.The FPGA BIST has no area overhead or performance reduction issues like conventional BIST.A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation.In this work,the Configurable Logic Blocks(CLBs)of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture.To evaluate the CLBs’capabilities including distributed modes of operation of Random Access Memory(RAM),several types of configurations are created.These setups have the ability to identify 100%stuck-at failures in every CLB.This method is suitable for all phases of FPGA testing and has no overhead or performance cost.展开更多
Objective To investigate effects of clenbuterol （CLB） on the peroxisome proliferators- activated receptor γ （PPARγ） expression in adipose tissues of rats. Methods Twenty adult female Sprague-Dawley rats were ran...Objective To investigate effects of clenbuterol （CLB） on the peroxisome proliferators- activated receptor γ （PPARγ） expression in adipose tissues of rats. Methods Twenty adult female Sprague-Dawley rats were randomly divided into 4 groups （5 rats per group）. CLB solved in normal saline solution was given at the dose of 0 mg/kg body weight （bw） （group A, as the control）, 0.4 mg/kg bw （group B, low-dose group）, 2.0 mg/kg bw （group C, mid-dose group）, and 18.5 mg/kg bw （group D, high-dose group）for 14 d by gavage consecutively, respectively. Methods of immunohistochemistry, quantitative Real-time PCR and Western blotting were performed to detect expression of PPARγ in the adipose tissue samples. Results PPARγ-positive immunostaining was strong in the controls and weak in the experimental groups. There was no difference on PPARγmRNA and protein between the low-dose group and the control （P〉0.05）. With the increase of CLB doses, expression levels of PPARγmRNA and protein were significantly lower in mid- or high-dose group than those in the control （19〈0.01）. Conclusions The PPARγ expression in adipose tissues of rats could be down-regulated after CLB exposure, and the decrease became more severe with the increasing doses.展开更多
A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured a...A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.展开更多
This article presents a proposal for a model of a microprogram control unit (CMCU) with output identification adapted for implementation in complex programmable logic devices (CPLD) equipped with integrated memory mod...This article presents a proposal for a model of a microprogram control unit (CMCU) with output identification adapted for implementation in complex programmable logic devices (CPLD) equipped with integrated memory modules [1]. An approach which applies two sources of code and one-hot encoding has been used in a base CMCU model with output identification [2] [3]. The article depicts a complete example of processing for the proposed CMCU model. Furthermore, it also discusses the advantages and disadvantages of the approach in question and presents the results of the experiments conducted on a real CPLD system.展开更多
A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited ifa large number of LUTs and multiplexers are presented. Since ...A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited ifa large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.展开更多
文摘本文以Xilinx公司基于SRAM的FPGA XC4010为研究对象,将FP- GA配置成两种电路来完成对可编程逻辑模块(CLB)的测试,并阐述了如何在Teradyne商用ATE(Automatic Test Equipment)J750上实现FPGA的在线配置及测试,为FPGA面向应用的测试提供一种有效的方法。
文摘FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.
基金supported by Science and Technology Planning Project of Guangzhou City,China(No.2013 00000114)
文摘Objective To investigate effects of clenbuterol （CLB） on testicular ultrastructure of rat. Methods Twenty adult male Sprague-Dawley rats were randomly divided into four groups （5 rats per group）. CLB solved in normal saline solution was given at the dose of O mg/kg body weight （bw） （group A, as control）, 0.4 mg/kg bw （group B）, 2.0 mg/kg bw （group C）, and 18.5 mg/kg bw （group D）for 14 d by garage consecutively, respectively. Transmission electron microscopy was used to observe changes on testicular ultrastructure. Results In group B, some small vacuoles were found in Sertoli cells. In groups C and D, vacuoles were common in Sertoli cells and spermatogonia. The phenomenon of vacuolation in group D was more severe than that in group C. In group D, basal membrane showed some irregular and wrinkled changes, Leydig cells had more vacuoles and increased lipid droplets. Conclusion Testicular ultrastructure of rat had pathological changes after CLB exposure, and the alterations became more severe with the increasing doses.
文摘Interconnected cells,Configurable Logic Blocks(CLBs),and input/output(I/O)pads are all present in every Field Programmable Gate Array(FPGA)structure.The interconnects are formed by the physical paths for connecting the blocks.The combinational and sequential circuits are used in the logic blocks to execute logical functions.The FPGA includes two different tests called interconnect testing and logical testing.Instead of using an additional circuitry,the Built-in-Self-Test(BIST)logic is coded into an FPGA,which is then reconfigured to perform its specific operation after the testing is completed.As a result,additional test circuits for the FPGA board are no longer required.The FPGA BIST has no area overhead or performance reduction issues like conventional BIST.A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation.In this work,the Configurable Logic Blocks(CLBs)of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture.To evaluate the CLBs’capabilities including distributed modes of operation of Random Access Memory(RAM),several types of configurations are created.These setups have the ability to identify 100%stuck-at failures in every CLB.This method is suitable for all phases of FPGA testing and has no overhead or performance cost.
基金supported by Science and Technology Planning Project of Guangzhou City,China(No.201300000114)
文摘Objective To investigate effects of clenbuterol （CLB） on the peroxisome proliferators- activated receptor γ （PPARγ） expression in adipose tissues of rats. Methods Twenty adult female Sprague-Dawley rats were randomly divided into 4 groups （5 rats per group）. CLB solved in normal saline solution was given at the dose of 0 mg/kg body weight （bw） （group A, as the control）, 0.4 mg/kg bw （group B, low-dose group）, 2.0 mg/kg bw （group C, mid-dose group）, and 18.5 mg/kg bw （group D, high-dose group）for 14 d by gavage consecutively, respectively. Methods of immunohistochemistry, quantitative Real-time PCR and Western blotting were performed to detect expression of PPARγ in the adipose tissue samples. Results PPARγ-positive immunostaining was strong in the controls and weak in the experimental groups. There was no difference on PPARγmRNA and protein between the low-dose group and the control （P〉0.05）. With the increase of CLB doses, expression levels of PPARγmRNA and protein were significantly lower in mid- or high-dose group than those in the control （19〈0.01）. Conclusions The PPARγ expression in adipose tissues of rats could be down-regulated after CLB exposure, and the decrease became more severe with the increasing doses.
基金Project supported by the National High Technology Research and Development Program of China (No.2007AA01Z285)the National Natural Science Foundation of China (No.60876015)
文摘A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.
文摘This article presents a proposal for a model of a microprogram control unit (CMCU) with output identification adapted for implementation in complex programmable logic devices (CPLD) equipped with integrated memory modules [1]. An approach which applies two sources of code and one-hot encoding has been used in a base CMCU model with output identification [2] [3]. The article depicts a complete example of processing for the proposed CMCU model. Furthermore, it also discusses the advantages and disadvantages of the approach in question and presents the results of the experiments conducted on a real CPLD system.
文摘A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited ifa large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.
