Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% o...Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.展开更多
As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled ...As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design（TCAD） simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.展开更多
随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减D...随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减DVS(Dynamic Voltage Scaling)和动态阈值电压缩减DVTS(Dynamic VTH Scaling)的方法,其中DVTS又是通过对衬底偏压的调整来实现阈值电压的调制的.本文重点研究了这两种技术的原理和实现结构,并分析了它们目前的研究和应用。展开更多
Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse q...Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.展开更多
A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard f...A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.展开更多
文摘Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
文摘As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design（TCAD） simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.
文摘随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减DVS(Dynamic Voltage Scaling)和动态阈值电压缩减DVTS(Dynamic VTH Scaling)的方法,其中DVTS又是通过对衬底偏压的调整来实现阈值电压的调制的.本文重点研究了这两种技术的原理和实现结构,并分析了它们目前的研究和应用。
基金supported by the National Natural Science Foundation of China(Grant Nos.61376109,61434007,and 61176030)
文摘Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.
基金Project supported by the National Natural Science Foundation of China(No.60976023)the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)
文摘A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.
