An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its su...An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.展开更多
In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challengin...In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challenging issue of how to obtain single protocol data frames from multiprotocol data frames. It can improve accuracy and efficiency by similarity between bit-stream data frames and clusters,extract clusters in the process of clustering. Every cluster obtained contains similarity evaluation index which is helpful to evaluation. More importantly,IAGNES algorithm can automatically recognize the number of cluster. Experiments on the data set published by Lincoln Laboratory shows that the algorithm can cluster the protocol data frames with high accuracy.展开更多
The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-s...The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.展开更多
基金supported by the National Natural Science Foundation of China(No.60576028)
文摘An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.
基金Supported by the National Natural Science Foundation of China(No.F020704)
文摘In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challenging issue of how to obtain single protocol data frames from multiprotocol data frames. It can improve accuracy and efficiency by similarity between bit-stream data frames and clusters,extract clusters in the process of clustering. Every cluster obtained contains similarity evaluation index which is helpful to evaluation. More importantly,IAGNES algorithm can automatically recognize the number of cluster. Experiments on the data set published by Lincoln Laboratory shows that the algorithm can cluster the protocol data frames with high accuracy.
基金Project supported by the National Natural Science Foundation of China(No.60576028).
文摘The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
