We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel me...We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.展开更多
In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
在过去的20年里,史蒂夫先生每天早上都会来到当地的同一家餐厅,坐在同一个位置,点同样的早餐。Steve Bellissimo,lovingly known as Mr Steve,shares a special relationship with his local Chick⁃fil⁃A.The resident is so much more ...在过去的20年里,史蒂夫先生每天早上都会来到当地的同一家餐厅,坐在同一个位置,点同样的早餐。Steve Bellissimo,lovingly known as Mr Steve,shares a special relationship with his local Chick⁃fil⁃A.The resident is so much more than the average customer;hes become a part of the restaurants family.For the last 20 years,Mr Steve has come into his local Chick⁃fil⁃A every morning.He sits in the same booth(小间)and orders the same breakfast.展开更多
A Good Man Is Hard to Find is a famous fiction which attracts many scholars to analyze the characters of the protagonists. According to Booth's rhetorical theory, it tries to analyze how the rhetorical skills infl...A Good Man Is Hard to Find is a famous fiction which attracts many scholars to analyze the characters of the protagonists. According to Booth's rhetorical theory, it tries to analyze how the rhetorical skills influence the readers'interpretation to the work by analyzing the application of narrative visual conversion, irony and foreshadowing. It will help readers understand the full fiction better.展开更多
We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multipli...We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.展开更多
An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized...An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm × 132. 5μm area size has been achieved in 0. 18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area （about 23.52% reduction） and less delay than those of the common saturating MAC based on standard cell library.展开更多
Based on rhetorical research methods of the unreliability,the paper intends to explore the unreliable narrative strategies of the narrator in Grace Paley's The Loudest Voice from the perspectives of the Wayne Boot...Based on rhetorical research methods of the unreliability,the paper intends to explore the unreliable narrative strategies of the narrator in Grace Paley's The Loudest Voice from the perspectives of the Wayne Booth's criterion of the distance between the narrator and the implied author and James Phelan's extension of unreliability on the basis of classical rhetorical narratology,point⁃ing out that the unreliability serves as the narrative trap which is set up to reveal the inner theme of the work:"The loudest voice"-what the protagonist thought she certainly possessed was only her illusion instead of the truth,and Eastern European Jewish com⁃munity was de facto marginalized by the mainstream culture at that time.展开更多
The necessity and feasibility of the use of the personalized ventilation（PV）technology in a toll booth is described.First,the indoor environment of the toll booth equipped with a PV system is analyzed.Based on the a...The necessity and feasibility of the use of the personalized ventilation（PV）technology in a toll booth is described.First,the indoor environment of the toll booth equipped with a PV system is analyzed.Based on the analysis results,a set of equipment for controlling the indoor air quality（IAQ）of the toll booth is devised.Then,a full-scale model of the toll booth is set up in the laboratory.The airflow organization,the optimum operation parameters,and the restraint effects of the PV system on pollution are also experimentally studied.The experimental results on the air supply characteristics show that the PV system can effectively reduce the air age,improve the ventilation efficiency,and enhance the comfort and acceptability of human beings.In addition,this system plays a significant role in preventing pollution.展开更多
文摘We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
文摘在过去的20年里,史蒂夫先生每天早上都会来到当地的同一家餐厅,坐在同一个位置,点同样的早餐。Steve Bellissimo,lovingly known as Mr Steve,shares a special relationship with his local Chick⁃fil⁃A.The resident is so much more than the average customer;hes become a part of the restaurants family.For the last 20 years,Mr Steve has come into his local Chick⁃fil⁃A every morning.He sits in the same booth(小间)and orders the same breakfast.
文摘A Good Man Is Hard to Find is a famous fiction which attracts many scholars to analyze the characters of the protagonists. According to Booth's rhetorical theory, it tries to analyze how the rhetorical skills influence the readers'interpretation to the work by analyzing the application of narrative visual conversion, irony and foreshadowing. It will help readers understand the full fiction better.
基金supported by the National Natural Science Foundation of China (No. 60776022)the Science and Technology Fund of Zhejiang Province (No. 2008C21166)+3 种基金the Key Scientific Research Fund of the Department of Education of Zhejiang Province (No. 20061666)the Professor Fund (No. JSL2007001)the Scientific Research Fund (No. XK0610030)the K. C. Wong Magna Fund in Ningbo University, China
文摘We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.
基金The National Natural Science Foundation of China(No.90407009),the National High Technology Research and Develop-ment Program of China(863Program) (No.2003AA1Z1340)
文摘An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm × 132. 5μm area size has been achieved in 0. 18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area （about 23.52% reduction） and less delay than those of the common saturating MAC based on standard cell library.
文摘Based on rhetorical research methods of the unreliability,the paper intends to explore the unreliable narrative strategies of the narrator in Grace Paley's The Loudest Voice from the perspectives of the Wayne Booth's criterion of the distance between the narrator and the implied author and James Phelan's extension of unreliability on the basis of classical rhetorical narratology,point⁃ing out that the unreliability serves as the narrative trap which is set up to reveal the inner theme of the work:"The loudest voice"-what the protagonist thought she certainly possessed was only her illusion instead of the truth,and Eastern European Jewish com⁃munity was de facto marginalized by the mainstream culture at that time.
文摘The necessity and feasibility of the use of the personalized ventilation（PV）technology in a toll booth is described.First,the indoor environment of the toll booth equipped with a PV system is analyzed.Based on the analysis results,a set of equipment for controlling the indoor air quality（IAQ）of the toll booth is devised.Then,a full-scale model of the toll booth is set up in the laboratory.The airflow organization,the optimum operation parameters,and the restraint effects of the PV system on pollution are also experimentally studied.The experimental results on the air supply characteristics show that the PV system can effectively reduce the air age,improve the ventilation efficiency,and enhance the comfort and acceptability of human beings.In addition,this system plays a significant role in preventing pollution.
