Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题...基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题的困扰。本文基于标准0.18μm BCD工艺,开展了18 V NLDMOS器件总剂量辐射效应研究,提出了一种总剂量辐射加固工艺技术。采用离子注入和材料改性技术工艺,提高了浅槽隔离场区边缘的P型硅反型阈值,从而增强了NLDMOS器件的抗辐射能力。通过对比实验表明,当辐照总剂量为100 krad(Si)时,加固的NLDMOS器件的抗辐射性能明显优于非加固的器件。通过总剂量辐射加固工艺技术的研究,可有效提高器件的抗总剂量辐射能力,避免设计加固造成芯片面积增大的问题。展开更多
Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique wa...Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.展开更多
To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing...To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed circuit is implemented;the active die area is 0.17×0.20 mm;. Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from -40 to 150℃,the power supply rejection ratio is -98.2 dB,the line regulation is 0.3 mV/V,and the power consumption is only 0.38 mW.The proposed bandgap voltage reference has good characteristics such as small area,low power consumption, good temperature stability,high power supply rejection ratio,as well as low line regulation.This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog,digital and mixed systems.展开更多
A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9...A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.展开更多
This paper presents a novel high precision and wide range adjustable LED constant-current drive controller design.Compared with the traditional technique,the conventional mirror resistance is substituted by a MOSFET w...This paper presents a novel high precision and wide range adjustable LED constant-current drive controller design.Compared with the traditional technique,the conventional mirror resistance is substituted by a MOSFET with fixed drain voltage,and a negative feedback amplifier is used to keep all mirror device voltages equal,so that the output current is precise and not affected by the load supply voltage.In addition,the electric property of the mirror MOSFET is optimized by a current subsection mirror（CSM） mechanism,thus ensuring a wide range of output current with high accuracy.A three-channel LED driver chip based on this project is designed and fabricated in the TSMC 0.6μm BCD process with a die area of 1.1×0.7 mm^2.Experimental results show that the proposed LED drive controller works well, and,as expected,the output current can be maintained from 5 to 60 mA.A relative current accuracy error of less than 1%and a maximal relative current matching error of 1.5%are successfully achieved.展开更多
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
文摘基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题的困扰。本文基于标准0.18μm BCD工艺,开展了18 V NLDMOS器件总剂量辐射效应研究,提出了一种总剂量辐射加固工艺技术。采用离子注入和材料改性技术工艺,提高了浅槽隔离场区边缘的P型硅反型阈值,从而增强了NLDMOS器件的抗辐射能力。通过对比实验表明,当辐照总剂量为100 krad(Si)时,加固的NLDMOS器件的抗辐射性能明显优于非加固的器件。通过总剂量辐射加固工艺技术的研究,可有效提高器件的抗总剂量辐射能力,避免设计加固造成芯片面积增大的问题。
文摘Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.
基金supported by the National Natural Science Foundation of China(Nos.60725415,60971066)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260)the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005)
文摘To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed circuit is implemented;the active die area is 0.17×0.20 mm;. Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from -40 to 150℃,the power supply rejection ratio is -98.2 dB,the line regulation is 0.3 mV/V,and the power consumption is only 0.38 mW.The proposed bandgap voltage reference has good characteristics such as small area,low power consumption, good temperature stability,high power supply rejection ratio,as well as low line regulation.This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog,digital and mixed systems.
文摘A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.
基金supported by the National Ministry Pre-Research Foundation of China(No.9140A08010208DZ0123)the Applied Materials Innovation Foundation of Xi'an,China(No.XA-AM-200817)
文摘This paper presents a novel high precision and wide range adjustable LED constant-current drive controller design.Compared with the traditional technique,the conventional mirror resistance is substituted by a MOSFET with fixed drain voltage,and a negative feedback amplifier is used to keep all mirror device voltages equal,so that the output current is precise and not affected by the load supply voltage.In addition,the electric property of the mirror MOSFET is optimized by a current subsection mirror（CSM） mechanism,thus ensuring a wide range of output current with high accuracy.A three-channel LED driver chip based on this project is designed and fabricated in the TSMC 0.6μm BCD process with a die area of 1.1×0.7 mm^2.Experimental results show that the proposed LED drive controller works well, and,as expected,the output current can be maintained from 5 to 60 mA.A relative current accuracy error of less than 1%and a maximal relative current matching error of 1.5%are successfully achieved.
