集成电路(IC,Integrated Circuit)作为信息产业的基础和核心,设计,测试与制造是其不可分割的几个方面。在通信领域内,模数转换器(Analog to Digital Converter,ADC)作为从模拟调制到数字基带的最后一级电路,分析和验证其性能是保证整个...集成电路(IC,Integrated Circuit)作为信息产业的基础和核心,设计,测试与制造是其不可分割的几个方面。在通信领域内,模数转换器(Analog to Digital Converter,ADC)作为从模拟调制到数字基带的最后一级电路,分析和验证其性能是保证整个芯片性能的重要手段。提出一种片内ADC电路自动测试平台的设计方法,并成功应用到某款无线连接芯片ADC测试中,促进了该芯片的量产。展开更多
采用7级子ADC流水线结构设计了一个8位80 Msample/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第1级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第1级子ADC的MDAC中,并且采用逐...采用7级子ADC流水线结构设计了一个8位80 Msample/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第1级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第1级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比(SNR)为49.5 d B,有效位数(ENOB)为7.98位,该ADC的芯片面积只有0.56 mm2,典型的功耗电流仅为22 m A。整个ADC性能达到设计要求。展开更多
The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect ...The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.展开更多
Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays...Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays far away from practical application.The lack of ASIC strictly limits the research and development of domestic high energy physics field.A 12-bit multichannel ADC designed for high density readout is introduced as a major candidate for solution.A precise model is discussed and the simulation fully agrees with the model,which indicates a key principle of design.Design is performed according to the given rule,and novel layout techniques are carried out.Measurement results in all aspects are also obtained,showing an excellent real performance,which satisfies the practical requirement.展开更多
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of t...This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.展开更多
文摘集成电路(IC,Integrated Circuit)作为信息产业的基础和核心,设计,测试与制造是其不可分割的几个方面。在通信领域内,模数转换器(Analog to Digital Converter,ADC)作为从模拟调制到数字基带的最后一级电路,分析和验证其性能是保证整个芯片性能的重要手段。提出一种片内ADC电路自动测试平台的设计方法,并成功应用到某款无线连接芯片ADC测试中,促进了该芯片的量产。
文摘采用7级子ADC流水线结构设计了一个8位80 Msample/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第1级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第1级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比(SNR)为49.5 d B,有效位数(ENOB)为7.98位,该ADC的芯片面积只有0.56 mm2,典型的功耗电流仅为22 m A。整个ADC性能达到设计要求。
基金the National Natural Science Foundation of China （60331010, 60271018）.
文摘The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.
基金supported by the National Natural Science Foundation of China (Grant No.10735060)
文摘Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays far away from practical application.The lack of ASIC strictly limits the research and development of domestic high energy physics field.A 12-bit multichannel ADC designed for high density readout is introduced as a major candidate for solution.A precise model is discussed and the simulation fully agrees with the model,which indicates a key principle of design.Design is performed according to the given rule,and novel layout techniques are carried out.Measurement results in all aspects are also obtained,showing an excellent real performance,which satisfies the practical requirement.
文摘This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
