The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the ...The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.展开更多
The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs bec...The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier(OTA) in ?∑ ADC design. This work aims to provide a summary of the fully VCO-based ?∑ ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based ?∑ ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.展开更多
By analyzing the theory of over-sampling and averaging, the conclusion is educed that white noise accompanies the signal and the addition of each bit of resolution can be achieved via a fourfold sampling frequency. Th...By analyzing the theory of over-sampling and averaging, the conclusion is educed that white noise accompanies the signal and the addition of each bit of resolution can be achieved via a fourfold sampling frequency. The addition of each bit will approximately increase the SNR （signal to noise ratio） to 6dB.展开更多
A 10 or 12 bit programmable successive approximation register（SAR） ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-do...A 10 or 12 bit programmable successive approximation register（SAR） ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio（SNDR） of 68 dB（11 ENOB）,a spurious free dynamic range（SFDR） of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.展开更多
介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率...介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。展开更多
In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC ...In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.展开更多
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low late...We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.展开更多
The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect ...The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.展开更多
LTE(long term evolution)及其后续演进已成为全球移动通信领域开发的热点。在LTE产业链中,终端射频测试是相对薄弱的环节;信道带宽的增大又对采样速率及硬件处理能力提出很高的要求,成为制约终端射频指标测试的瓶颈。在分析终端射频邻...LTE(long term evolution)及其后续演进已成为全球移动通信领域开发的热点。在LTE产业链中,终端射频测试是相对薄弱的环节;信道带宽的增大又对采样速率及硬件处理能力提出很高的要求,成为制约终端射频指标测试的瓶颈。在分析终端射频邻道泄漏功率比(adjacent channel leakage power ratio,ACLR)测试原理、测试方法及实现技术的基础上,提出一种通过修改测试仪表接收机射频本地振荡器频率来增大观测带宽、降低采样速率的测试方法。该测试方法具有很好的灵活性和可扩展性,大大降低测试成本,因此具有很大的市场应有价值。展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.10978017 and 61201288)Shaanxi Natural Science Foundation Research Plan Projects,China(Grant No.2014JM2-6128)Shaanxi Major Technological Achievements Transformation and Guidance Special Projects,China(Grant No.2015KTCG01-01)
文摘The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.
基金This work was supported by the National Natural Science Foundation of China (Nos. 61934009 and 62090042)Beijing National Research Center for Information Science and Technology, Beijing Innovation Center for Future Chips (ICFC)the Academician Expert Open Fund of Beijing Smart-chip Microelectronics Technology Co., Ltd.
文摘The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier(OTA) in ?∑ ADC design. This work aims to provide a summary of the fully VCO-based ?∑ ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based ?∑ ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.
文摘By analyzing the theory of over-sampling and averaging, the conclusion is educed that white noise accompanies the signal and the addition of each bit of resolution can be achieved via a fourfold sampling frequency. The addition of each bit will approximately increase the SNR （signal to noise ratio） to 6dB.
基金Project supported by the PhD Programs Foundation of the Ministry of Education of China (No.20111011315)the National Science and Technology Important Project of China (No.2010ZX03006-003-01)
文摘A 10 or 12 bit programmable successive approximation register（SAR） ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio（SNDR） of 68 dB（11 ENOB）,a spurious free dynamic range（SFDR） of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.
文摘介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。
文摘In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.
基金Project supported by the State Key Development Program for Basic Research of China(Grants Nos.2017YFA0304300 and 2016YFA0300600)the Natural Science Foundation of Beijing,China(Grant No.Z190012)+1 种基金the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2020B0303030001)the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB28000000).
文摘We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
基金the National Natural Science Foundation of China （60331010, 60271018）.
文摘The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.
文摘LTE(long term evolution)及其后续演进已成为全球移动通信领域开发的热点。在LTE产业链中,终端射频测试是相对薄弱的环节;信道带宽的增大又对采样速率及硬件处理能力提出很高的要求,成为制约终端射频指标测试的瓶颈。在分析终端射频邻道泄漏功率比(adjacent channel leakage power ratio,ACLR)测试原理、测试方法及实现技术的基础上,提出一种通过修改测试仪表接收机射频本地振荡器频率来增大观测带宽、降低采样速率的测试方法。该测试方法具有很好的灵活性和可扩展性,大大降低测试成本,因此具有很大的市场应有价值。
