The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentrati...The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.展开更多
According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the...Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.展开更多
文摘The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
文摘Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.
