Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. ...Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.展开更多
While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one wa...While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.展开更多
基金Supported by NNSF of China(Key International Cooperative Project No.60010121219)
文摘Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.
文摘While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.
