Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is ...Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is linear correlation between the generation of interface traps and SILC for both types of MOSFET with different channel lengths (including 1,0.5,0.275,and 0.135μm) and different gate oxide thickness (4nm and 2.5nm).These experimental evidences show that the SILC has a strong dependence on interface traps.展开更多
The degradation of device parameters and the degradation of the stress induced leakage current （SILC） of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with...The degradation of device parameters and the degradation of the stress induced leakage current （SILC） of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1. 4nm gate oxides. Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling （DT） stresses. A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.展开更多
A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage curre...A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.展开更多
文摘Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is linear correlation between the generation of interface traps and SILC for both types of MOSFET with different channel lengths (including 1,0.5,0.275,and 0.135μm) and different gate oxide thickness (4nm and 2.5nm).These experimental evidences show that the SILC has a strong dependence on interface traps.
基金the National Natural Science Foundation of China(Nos.60736033,60506020)~~
文摘The degradation of device parameters and the degradation of the stress induced leakage current （SILC） of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1. 4nm gate oxides. Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling （DT） stresses. A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.
文摘A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.
