This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and ...This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.展开更多
We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage c...We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage controlled oscillator （VCO） are employed in this design to realize the aforementioned properties. Measured results show that the experimental chip, implemented in a standard 0.5μm 5V CMOS logic process, has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.（dual-edge-triggered phase frequency detector）展开更多
文摘This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.
文摘We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage controlled oscillator （VCO） are employed in this design to realize the aforementioned properties. Measured results show that the experimental chip, implemented in a standard 0.5μm 5V CMOS logic process, has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.（dual-edge-triggered phase frequency detector）
