The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation res...The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.展开更多
用斜坡电压法(Voltage Ramp,V-ramp)评价了0·18μm双栅极CMOS工艺栅极氧化膜击穿电量(Charge toBreakdown,Qbd)和击穿电压(Voltage to Breakdown,Vbd).研究结果表明,低压器件(1·8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬...用斜坡电压法(Voltage Ramp,V-ramp)评价了0·18μm双栅极CMOS工艺栅极氧化膜击穿电量(Charge toBreakdown,Qbd)和击穿电压(Voltage to Breakdown,Vbd).研究结果表明,低压器件(1·8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小,而高压器件(3·3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大,击穿电压测试值也发现与击穿电量相似的现象.其原因可以归结为由于光刻工艺对多晶硅/厚氧界面的损伤.该损伤使多晶硅/厚氧界面产生大量的界面态.从而造成了薄氧与厚氧n衬底和p衬底MOS电容击穿电量差的不同.从Weibull分布来看,击穿电压Weibull分布斜率比击穿电量.击穿电压的分布非常均匀,而且所有样品的失效模式都为本征失效,没有看到“尾巴”,说明工艺非常稳定.展开更多
文摘The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.
文摘用斜坡电压法(Voltage Ramp,V-ramp)评价了0·18μm双栅极CMOS工艺栅极氧化膜击穿电量(Charge toBreakdown,Qbd)和击穿电压(Voltage to Breakdown,Vbd).研究结果表明,低压器件(1·8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小,而高压器件(3·3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大,击穿电压测试值也发现与击穿电量相似的现象.其原因可以归结为由于光刻工艺对多晶硅/厚氧界面的损伤.该损伤使多晶硅/厚氧界面产生大量的界面态.从而造成了薄氧与厚氧n衬底和p衬底MOS电容击穿电量差的不同.从Weibull分布来看,击穿电压Weibull分布斜率比击穿电量.击穿电压的分布非常均匀,而且所有样品的失效模式都为本征失效,没有看到“尾巴”,说明工艺非常稳定.
