As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time,...As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.展开更多
利用调节型共源共栅电路结构(RGC)可以使跨阻放大器得到较高的带宽,并且通过级联并联-并联负反馈电路可以使增益得到提高。采用0.5μm的标准互补型金属氧化物半导体(CMOS)工艺进行设计,仿真。测试结果表明,该电路具有69.93 d B的跨阻增...利用调节型共源共栅电路结构(RGC)可以使跨阻放大器得到较高的带宽,并且通过级联并联-并联负反馈电路可以使增益得到提高。采用0.5μm的标准互补型金属氧化物半导体(CMOS)工艺进行设计,仿真。测试结果表明,该电路具有69.93 d B的跨阻增益,830 MHz的-3 dB带宽。在输入电流为1μA时,其输出电压的动态摆幅达到4.5 mV,在5 V电源电压下功耗仅为63.16 mW。展开更多
This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-T...This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.展开更多
A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(V...A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.展开更多
A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to pe...A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to perform auto-gaincontrol and threshold extraction. Regulated cascade （RGC） architecture is exploited as the input stage to reduce the input impedance of the circuit and isolate the large parasitic capacitance including the photodiode capacitance from the determination pole, thus increasing the bandwidth. This preamplifier is implemented using the low-cost 0. 13 ixm CMOS technology. The die area is 425 μm × 475 μm and the total power dissipation is 23.4 mW. The test results indicate that the preamplifier can work at a speed from 1.25 to 10.312 5 Gbit/s, providing a high transimpedance gain of 64.0 dBΩ and a low gain of 54. 6 dBl2 with a dynamic input range of over 22.9 dB. The equivalent input noise current is 23. 4 pA/ Hz1/2. The proposed burst amplifier satisfies related specifications defined in 10G-EPON and XG-PON standards.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61376033,61006028)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory
文摘As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.
基金supported in part by Research and Development Program in Key Areas of Guangdong Province under Grant 2019B010116002in part by the National Natural Science Foundation of China under Grant 62074074in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.
基金The National Natural Science Foundation of China(No.61306069)
文摘A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.
基金The Key Technology Research and Development Program of Jiangsu Province ( No. BE2008128)
文摘A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to perform auto-gaincontrol and threshold extraction. Regulated cascade （RGC） architecture is exploited as the input stage to reduce the input impedance of the circuit and isolate the large parasitic capacitance including the photodiode capacitance from the determination pole, thus increasing the bandwidth. This preamplifier is implemented using the low-cost 0. 13 ixm CMOS technology. The die area is 425 μm × 475 μm and the total power dissipation is 23.4 mW. The test results indicate that the preamplifier can work at a speed from 1.25 to 10.312 5 Gbit/s, providing a high transimpedance gain of 64.0 dBΩ and a low gain of 54. 6 dBl2 with a dynamic input range of over 22.9 dB. The equivalent input noise current is 23. 4 pA/ Hz1/2. The proposed burst amplifier satisfies related specifications defined in 10G-EPON and XG-PON standards.
