This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratio...This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.展开更多
With the wide application of electronic hardware in aircraft such as air-to-ground communication,satellite communication,positioning system and so on,aircraft hardware is facing great secure pressure.Focusing on the s...With the wide application of electronic hardware in aircraft such as air-to-ground communication,satellite communication,positioning system and so on,aircraft hardware is facing great secure pressure.Focusing on the secure problem of aircraft hardware,this paper proposes a supervisory control architecture based on secure System-on-a-Chip(So C)system.The proposed architecture is attack-immune and trustworthy,which can support trusted escrow application and Dynamic Integrity Measurement(DIM)without interference.This architecture is characterized by a Trusted Monitoring System(TMS)hardware isolated from the Main Processor System(MPS),a secure access channel from TMS to the running memory of the MPS,and the channel is unidirectional.Based on this architecture,the DIM program running on TMS is used to measure and call the Lightweight Measurement Agent(LMA)program running on MPS.By this method,the Operating System(OS)kernel,key software and data of the MPS can be dynamically measured without disturbance,which makes it difficult for adversaries to attack through software.Besides,this architecture has been fully verified on FPGA prototype system.Compared with the existing systems,our architecture achieves higher security and is more efficient on DIM,which can fully supervise the running of application and aircraft hardware OS.展开更多
针对国内RISC-V(Reduced Instruction Set Computer-Five)处理器领域的空白以及对处理器性能的优化问题,将开源3级流水线RISC-V处理器VScale扩展为5级流水线处理器。在对比3级流水线和5级流水线的差异的基础上,为5级流水线设计了冒险检...针对国内RISC-V(Reduced Instruction Set Computer-Five)处理器领域的空白以及对处理器性能的优化问题,将开源3级流水线RISC-V处理器VScale扩展为5级流水线处理器。在对比3级流水线和5级流水线的差异的基础上,为5级流水线设计了冒险检测以及旁路单元,解决了5级流水线的数据相关问题,并为该处理器编写外设(LCD1602、UART)控制器,最终在FPGA(Field-Programmable Gate Array)开发板上实现了软硬件协同仿真。仿真结果表明,扩展后的处理器运行正常,且速度比扩展前的处理器快约30%。展开更多
基金国家自然科学基金，the Sci. & Technol. Project of Beijing，中国科学院资助项目，Synopsys公司资助项目
文摘This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.
基金supported by the National Key Research and Development Program of China(No.2017YFB0802502)by the Aeronautical Science Foundation(No.2017ZC51038)+4 种基金by the National Natural Science Foundation of China(Nos.62002006,61702028,61672083,61370190,61772538,61532021,61472429,and 61402029)by the Foundation of Science and Technology on Information Assurance Laboratory(No.1421120305162112006)by the National Cryptography Development Fund(No.MMJJ20170106)by the Defense Industrial Technology Development Program(No.JCKY2016204A102)by the Liaoning Collaboration Innovation Center For CSLE,China。
文摘With the wide application of electronic hardware in aircraft such as air-to-ground communication,satellite communication,positioning system and so on,aircraft hardware is facing great secure pressure.Focusing on the secure problem of aircraft hardware,this paper proposes a supervisory control architecture based on secure System-on-a-Chip(So C)system.The proposed architecture is attack-immune and trustworthy,which can support trusted escrow application and Dynamic Integrity Measurement(DIM)without interference.This architecture is characterized by a Trusted Monitoring System(TMS)hardware isolated from the Main Processor System(MPS),a secure access channel from TMS to the running memory of the MPS,and the channel is unidirectional.Based on this architecture,the DIM program running on TMS is used to measure and call the Lightweight Measurement Agent(LMA)program running on MPS.By this method,the Operating System(OS)kernel,key software and data of the MPS can be dynamically measured without disturbance,which makes it difficult for adversaries to attack through software.Besides,this architecture has been fully verified on FPGA prototype system.Compared with the existing systems,our architecture achieves higher security and is more efficient on DIM,which can fully supervise the running of application and aircraft hardware OS.
