A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are pre...A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are presented. Being different from traditional techniques, this idea focuses on finding multiple temperatures in the whole range at which the first order derivatives of the output reference voltage equal zero. In this way, the curve of the output reference voltage is flattened and a better effect of curvature compensation is achieved. The circuitry is simulated in ST Microelectronics 0. 18μm CMOS technology, and the simulated result shows that the average temperature coefficient is only 1ppm/℃ in the range from - 40 to 125℃.展开更多
AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment pr...AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment protocol in diabetic macuiar edema（DME）.METHODS：A comprehensive literature search using the Cochrane Collaboration methodology to identify RCTs comparing SDM with mETDRS for DME.The participants were type Ⅰ or type Ⅱ diabetes mellitus with clinically significant macuiar edema treated by SDM from previously reported randomized controlled trials（RCTs）.The primary outcome measures were the changes in the best corrected visual acuity（BCVA） and the central macuiar thickness（CMT） as measured by optical coherence tomography（OCT）.The secondary outcomes were the contrast sensitivity and the damages of the retina.RESULTS：Seven studies were identified and analyzed for comparing SDM（215 eyes） with mETDRS（210 eyes）for DME.There were no statistical differences in the BCVA after treatment between the SDM and mETDRS based on the follow-up：3mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.77）,6mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.75）,12mo（MD,-0.05;95% Cl,-0.17 to 0.07;P=0.40）.Likewise,there were no statistical differences in the CMT after treatment between the SDM and mETDRS in 3mo（MD,-9.92;95% Cl,-28.69 to 8.85;P=0.30）,6mo（MD,-11.37;95% Cl,-29.65 to 6.91;P=0.22）,12mo（MD,8.44;95% Cl,-29.89 to 46.77;P=0.67）.Three RCTs suggested that SDM laser results in good preservation of contrast sensitivity as mETDRS,in two different followup evaluations：3mo（MD,0.05;95% Cl,0 to 0.09;P=0.04） and 6mo（MD,0.02;95% Cl,-0.10 to 0.14;P=0.78）.Two RCTs showed that the SDM laser treatment did less retinal damage than that mETDRS did（OR,0.05;95% Cl,0.02 to 0.13;P〈0.01）.CONCLUSION：SDM laser photocoagulation shows an equally good effect on visual acuity,contrast sensitivity,and reduction of DME as compared to conventional mETDRS protocol with less retinal damage.展开更多
分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为...分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为线性区MOS管提供偏压以进一步降低功耗。基于SMIC 0.18μm CMOS工艺设计电路。仿真结果表明此电路在1.8 V电源电压下,–50^+150℃的温度系数为22.6×10–6/℃,基准电压源输出电压约为992 m V,25℃时静态电流为327.3 n A,电路总静态功耗为0.59μW,10 k Hz时的电源抑制比为–25.36 d B。展开更多
This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% o...Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.展开更多
To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it i...To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.展开更多
‘Neurodevelopmental disorders’comprise a group of congenital or acquired longterm conditions that are attributed to disturbance of the brain and or neuromuscular system and create functional limitations,including au...‘Neurodevelopmental disorders’comprise a group of congenital or acquired longterm conditions that are attributed to disturbance of the brain and or neuromuscular system and create functional limitations,including autism spectrum disorder,attention deficit/hyperactivity disorder,tic disorder/Tourette’s syndrome,developmental language disorders and intellectual disability.Cerebral palsy and epilepsy are often associated with these conditions within the broader framework of paediatric neurodisability.Co-occurrence with each other and with other mental health disorders including anxiety and mood disorders and behavioural disturbance is often the norm.Together these are referred to as neurodevelopmental,emotional,behavioural,and intellectual disorders(NDEBIDs)in this paper.Varying prevalence rates for NDEBID have been reported in developed countries,up to 15%,based on varying methodologies and definitions.NDEBIDs are commonly managed by either child health paediatricians or child/adolescent mental health(CAMH)professionals,working within multidisciplinary teams alongside social care,education,allied healthcare practitioners and voluntary sector.Fragmented services are common problems for children and young people with multi-morbidity,and often complicated by subthreshold diagnoses.Despite repeated reviews,limited consensus among clinicians about classification of the various NDEBIDs may hamper service improvement based upon research.The recently developed“Mental,Behavioural and Neurodevelopmental disorder”chapter of the International Classification of Diseases-11 offers a way forward.In this narrative review we search the extant literature and discussed a brief overview of the aetiology and prevalence of NDEBID,enumerate common problems associated with current classification systems and provide recommendations for a more integrated approach to the nosology and clinical care of these related conditions.展开更多
文摘A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are presented. Being different from traditional techniques, this idea focuses on finding multiple temperatures in the whole range at which the first order derivatives of the output reference voltage equal zero. In this way, the curve of the output reference voltage is flattened and a better effect of curvature compensation is achieved. The circuitry is simulated in ST Microelectronics 0. 18μm CMOS technology, and the simulated result shows that the average temperature coefficient is only 1ppm/℃ in the range from - 40 to 125℃.
文摘AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment protocol in diabetic macuiar edema（DME）.METHODS：A comprehensive literature search using the Cochrane Collaboration methodology to identify RCTs comparing SDM with mETDRS for DME.The participants were type Ⅰ or type Ⅱ diabetes mellitus with clinically significant macuiar edema treated by SDM from previously reported randomized controlled trials（RCTs）.The primary outcome measures were the changes in the best corrected visual acuity（BCVA） and the central macuiar thickness（CMT） as measured by optical coherence tomography（OCT）.The secondary outcomes were the contrast sensitivity and the damages of the retina.RESULTS：Seven studies were identified and analyzed for comparing SDM（215 eyes） with mETDRS（210 eyes）for DME.There were no statistical differences in the BCVA after treatment between the SDM and mETDRS based on the follow-up：3mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.77）,6mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.75）,12mo（MD,-0.05;95% Cl,-0.17 to 0.07;P=0.40）.Likewise,there were no statistical differences in the CMT after treatment between the SDM and mETDRS in 3mo（MD,-9.92;95% Cl,-28.69 to 8.85;P=0.30）,6mo（MD,-11.37;95% Cl,-29.65 to 6.91;P=0.22）,12mo（MD,8.44;95% Cl,-29.89 to 46.77;P=0.67）.Three RCTs suggested that SDM laser results in good preservation of contrast sensitivity as mETDRS,in two different followup evaluations：3mo（MD,0.05;95% Cl,0 to 0.09;P=0.04） and 6mo（MD,0.02;95% Cl,-0.10 to 0.14;P=0.78）.Two RCTs showed that the SDM laser treatment did less retinal damage than that mETDRS did（OR,0.05;95% Cl,0.02 to 0.13;P〈0.01）.CONCLUSION：SDM laser photocoagulation shows an equally good effect on visual acuity,contrast sensitivity,and reduction of DME as compared to conventional mETDRS protocol with less retinal damage.
文摘分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为线性区MOS管提供偏压以进一步降低功耗。基于SMIC 0.18μm CMOS工艺设计电路。仿真结果表明此电路在1.8 V电源电压下,–50^+150℃的温度系数为22.6×10–6/℃,基准电压源输出电压约为992 m V,25℃时静态电流为327.3 n A,电路总静态功耗为0.59μW,10 k Hz时的电源抑制比为–25.36 d B。
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
文摘Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
文摘To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.
文摘‘Neurodevelopmental disorders’comprise a group of congenital or acquired longterm conditions that are attributed to disturbance of the brain and or neuromuscular system and create functional limitations,including autism spectrum disorder,attention deficit/hyperactivity disorder,tic disorder/Tourette’s syndrome,developmental language disorders and intellectual disability.Cerebral palsy and epilepsy are often associated with these conditions within the broader framework of paediatric neurodisability.Co-occurrence with each other and with other mental health disorders including anxiety and mood disorders and behavioural disturbance is often the norm.Together these are referred to as neurodevelopmental,emotional,behavioural,and intellectual disorders(NDEBIDs)in this paper.Varying prevalence rates for NDEBID have been reported in developed countries,up to 15%,based on varying methodologies and definitions.NDEBIDs are commonly managed by either child health paediatricians or child/adolescent mental health(CAMH)professionals,working within multidisciplinary teams alongside social care,education,allied healthcare practitioners and voluntary sector.Fragmented services are common problems for children and young people with multi-morbidity,and often complicated by subthreshold diagnoses.Despite repeated reviews,limited consensus among clinicians about classification of the various NDEBIDs may hamper service improvement based upon research.The recently developed“Mental,Behavioural and Neurodevelopmental disorder”chapter of the International Classification of Diseases-11 offers a way forward.In this narrative review we search the extant literature and discussed a brief overview of the aetiology and prevalence of NDEBID,enumerate common problems associated with current classification systems and provide recommendations for a more integrated approach to the nosology and clinical care of these related conditions.
