分析了目前分段电流舵数模转换器（DAC）在动态性能提升和芯片面积缩小等方面的局限性。提出了动态元件匹配（DEM）译码技术。设计了16 bit DAC中的DEM译码电路结构,分析了DEM译码技术的原理。对该16 bit DAC的动态性能等进行了详细仿真...分析了目前分段电流舵数模转换器（DAC）在动态性能提升和芯片面积缩小等方面的局限性。提出了动态元件匹配（DEM）译码技术。设计了16 bit DAC中的DEM译码电路结构,分析了DEM译码技术的原理。对该16 bit DAC的动态性能等进行了详细仿真,并完成了整体版图设计。该DAC核心部分芯片面积仅为2. 2 mm^2。采用0. 18μm CMOS工艺完成了该DAC的加工和性能参数测试。在1 GHz采样率和100 MHz输入信号频率条件下,该DAC的无杂散动态范围约为67 dB,三阶互调失真约为76 dB,整体性能优于目前同类研究成果。展开更多
针对目前常用的基于参数化非线性模型(Parameterized Nonlinear Model,PNM)的补偿算法存在易陷入局部最小值,导致补偿性能不稳的问题,该文提出了基于最小二乘支持向量机(Least Squares Support Vector Machine,LS-SVM)的宽带接收前端非...针对目前常用的基于参数化非线性模型(Parameterized Nonlinear Model,PNM)的补偿算法存在易陷入局部最小值,导致补偿性能不稳的问题,该文提出了基于最小二乘支持向量机(Least Squares Support Vector Machine,LS-SVM)的宽带接收前端非线性补偿算法.该算法基于减谱-时频变换法(Spectrum Reduction Algorithm based on Time-Frequency Conversion,SRA-TFC)盲分离接收前端输出信号中的大功率基波信号和其他小功率信号,并以此作为LS-SVM逆模型的训练输入-输出样本对.引入最小二乘支持向量回归(Least Squares Support Vector Regression,LS-SVR)算法高精度拟合接收前端非线性逆模型.通过以宽带接收前端的输出信号为测试样本消除其非线性失真分量.仿真与实测结果表明:该算法可使宽带接收前端的无杂散失真动态范围(Spurs-Free-Dynamic-Range,SFDR)提高约20 dB,较基于PNM的补偿算法提高了约5 dB.展开更多
A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plu...A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.展开更多
This paper proposes a method to improve the spu-rious-free dynamic ranges(SFDRs)of 1-bit sampled signals greatly,which is very beneficial to multi-tone signals detection.Firstly,the relationship between the fundamenta...This paper proposes a method to improve the spu-rious-free dynamic ranges(SFDRs)of 1-bit sampled signals greatly,which is very beneficial to multi-tone signals detection.Firstly,the relationship between the fundamental component and the third harmonic component of 1-bit sampled signals is analyzed for determining four contiguous special frequency bands,which do not contain any third harmonics inside and co-ver 77.8%of the whole Nyquist sampling frequency band.Then,we present a special 4-channel monobit receiver model,where appropriate filter banks are used to obtain four desired pass bands before 1-bit quantization and each channel can sample and process sampled data independently to achieve a good in-stantaneous dynamic range without sacrificing the real-time per-formance or computing resources.The simulation results show that the proposed method effectively eliminates the effect of the most harmonics on SFDRs and the mean SFDR is increased to to 20 dB.Besides,the multi-signals simulation results indicate that the maximum amplitude separation(dynamic range)of two signals in each channel is 12 dB while the proposed monobit re-ceiver can deal with up to eight simultaneous arrival signals.In general,the designing method proposed in this paper has a po-tential engineering value.展开更多
文摘针对目前常用的基于参数化非线性模型(Parameterized Nonlinear Model,PNM)的补偿算法存在易陷入局部最小值,导致补偿性能不稳的问题,该文提出了基于最小二乘支持向量机(Least Squares Support Vector Machine,LS-SVM)的宽带接收前端非线性补偿算法.该算法基于减谱-时频变换法(Spectrum Reduction Algorithm based on Time-Frequency Conversion,SRA-TFC)盲分离接收前端输出信号中的大功率基波信号和其他小功率信号,并以此作为LS-SVM逆模型的训练输入-输出样本对.引入最小二乘支持向量回归(Least Squares Support Vector Regression,LS-SVR)算法高精度拟合接收前端非线性逆模型.通过以宽带接收前端的输出信号为测试样本消除其非线性失真分量.仿真与实测结果表明:该算法可使宽带接收前端的无杂散失真动态范围(Spurs-Free-Dynamic-Range,SFDR)提高约20 dB,较基于PNM的补偿算法提高了约5 dB.
文摘A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.
文摘This paper proposes a method to improve the spu-rious-free dynamic ranges(SFDRs)of 1-bit sampled signals greatly,which is very beneficial to multi-tone signals detection.Firstly,the relationship between the fundamental component and the third harmonic component of 1-bit sampled signals is analyzed for determining four contiguous special frequency bands,which do not contain any third harmonics inside and co-ver 77.8%of the whole Nyquist sampling frequency band.Then,we present a special 4-channel monobit receiver model,where appropriate filter banks are used to obtain four desired pass bands before 1-bit quantization and each channel can sample and process sampled data independently to achieve a good in-stantaneous dynamic range without sacrificing the real-time per-formance or computing resources.The simulation results show that the proposed method effectively eliminates the effect of the most harmonics on SFDRs and the mean SFDR is increased to to 20 dB.Besides,the multi-signals simulation results indicate that the maximum amplitude separation(dynamic range)of two signals in each channel is 12 dB while the proposed monobit re-ceiver can deal with up to eight simultaneous arrival signals.In general,the designing method proposed in this paper has a po-tential engineering value.
