This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the c...This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.展开更多
In this paper,an interleaved LCLC converter with enhancement-mode(E-mode)GaN devices is introduced to achieve the accurate current sharing performance for data center applications. Any tolerance in the resonant tank e...In this paper,an interleaved LCLC converter with enhancement-mode(E-mode)GaN devices is introduced to achieve the accurate current sharing performance for data center applications. Any tolerance in the resonant tank elements can lead to large load imbalance between any two different phases. Due to the steep gain curves of LCLC converters,conventional current sharing methods are not effective. In the proposed converter,the impedances of the resonant networks are matched by switching a capacitor,i.e.,switch controlled capacitor(SCC),in series with the resonant capacitor in one or some of the phases,which results in accurate load current sharing among the phases with an accuracy around 0.025%. The load share of a phase is sensed through the resonant current on it,and the control logic applied to such current sharing can be achieved. By this method,accurate current sharing is achieved for a wide input voltage range required for the hold-up time in data center applications. Interleaving is applied in the proposed multiphase LCLC converter,resulting in low current stress on the output capacitor and allowing ceramic capacitor implementation. Moreover,phase shedding accomplishes high light load efficiency. The performance of the proposed interleaved LCLC converter is verified by a two-phase 1 k W prototype with an input voltage ranging from 250 V to 400 V and a fixed 12 V output voltage.展开更多
A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
输入串联输出并联(inputseriesoutputparallel,ISOP)双有源桥(dualactivebridge,DAB)变换器的输入均压(input voltage sharing,IVS)主动控制策略存在控制系统复杂和传感器数量较多的问题。相反地,无源调控方法的控制系统简单,因而具有...输入串联输出并联(inputseriesoutputparallel,ISOP)双有源桥(dualactivebridge,DAB)变换器的输入均压(input voltage sharing,IVS)主动控制策略存在控制系统复杂和传感器数量较多的问题。相反地,无源调控方法的控制系统简单,因而具有明显的优势。基于无源均压思想,提出一种适用于共占空比控制的基于耦合电容的ISOP-DAB变换器的输入电压自平衡拓扑结构,通过耦合电容使得子模块的高频链环节产生电气耦合,从而实现子模块输入电压的均衡。进一步,给出含有耦合电容的ISOP-DAB变换器的简化等效电路,并进行理论分析与推导,得到子模块输入母线电压偏差及耦合电容电流与变换器硬件参数的关系。理论计算表明该拓扑在子模块参数存在较大的偏差时仍然具有较好的IVS能力。最后,仿真和实验结果验证该拓扑的可行性和有效性。展开更多
基金Project supported by the Natural Science Foundation for Key Program of Jiangsu Higher Education Institutions(No.09KJA510001)
文摘This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.
文摘In this paper,an interleaved LCLC converter with enhancement-mode(E-mode)GaN devices is introduced to achieve the accurate current sharing performance for data center applications. Any tolerance in the resonant tank elements can lead to large load imbalance between any two different phases. Due to the steep gain curves of LCLC converters,conventional current sharing methods are not effective. In the proposed converter,the impedances of the resonant networks are matched by switching a capacitor,i.e.,switch controlled capacitor(SCC),in series with the resonant capacitor in one or some of the phases,which results in accurate load current sharing among the phases with an accuracy around 0.025%. The load share of a phase is sensed through the resonant current on it,and the control logic applied to such current sharing can be achieved. By this method,accurate current sharing is achieved for a wide input voltage range required for the hold-up time in data center applications. Interleaving is applied in the proposed multiphase LCLC converter,resulting in low current stress on the output capacitor and allowing ceramic capacitor implementation. Moreover,phase shedding accomplishes high light load efficiency. The performance of the proposed interleaved LCLC converter is verified by a two-phase 1 k W prototype with an input voltage ranging from 250 V to 400 V and a fixed 12 V output voltage.
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
文摘输入串联输出并联(inputseriesoutputparallel,ISOP)双有源桥(dualactivebridge,DAB)变换器的输入均压(input voltage sharing,IVS)主动控制策略存在控制系统复杂和传感器数量较多的问题。相反地,无源调控方法的控制系统简单,因而具有明显的优势。基于无源均压思想,提出一种适用于共占空比控制的基于耦合电容的ISOP-DAB变换器的输入电压自平衡拓扑结构,通过耦合电容使得子模块的高频链环节产生电气耦合,从而实现子模块输入电压的均衡。进一步,给出含有耦合电容的ISOP-DAB变换器的简化等效电路,并进行理论分析与推导,得到子模块输入母线电压偏差及耦合电容电流与变换器硬件参数的关系。理论计算表明该拓扑在子模块参数存在较大的偏差时仍然具有较好的IVS能力。最后,仿真和实验结果验证该拓扑的可行性和有效性。
