In this paper, an attempt has been made to produce a recipient system of wireless charge for a simple hearing aid so that electrical signal would be generated through detecting and receiving radio frequency waves (RF)...In this paper, an attempt has been made to produce a recipient system of wireless charge for a simple hearing aid so that electrical signal would be generated through detecting and receiving radio frequency waves (RF). The purpose of this design is to receive wireless charge for hearing aids and basically for any electronic device which is not required to a high energy for being setup. In this study, it has been demonstrated that as the amount of radio receiving energy increases, distance of receiver from antenna should be decreased;otherwise, either maximum amount of the receiving energy, or signal power density of the transmitter should be increased. Since it is impossible to be performed, it is decided to set up an energy receiving system constructed by rectenna and charge Circuit and to adjust their parameters to provide energy requirements for a device with low-power consumption. In this paper, different components of an energy receiving system from radio frequency band have been mentioned and a diagram block has been suggested. Subsequently, input impedance of designed antenna has been adjusted by provided relations. This impedance should be adjusted with the total impedance of regarded hearing aid Circuit by which the highest amount of received signal power is transferred to the battery of hearing aids. Received signal is converted to a dc voltage by rectifier diode. Finally, by applying a voltage regulator which has been designed using a common-collector amplifier not only the output voltage is kept constant, but the power is also strengthened. The battery of the hearing aids will be charged using the obtained power and voltage.展开更多
This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate can ...This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate can resist high voltage, but whose source–gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 μm CDMOS technology. From the results, compared with the accuracy of16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover,power efficiency is up to 95% at 12 V input and 5 V output.展开更多
A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ...A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.展开更多
文摘In this paper, an attempt has been made to produce a recipient system of wireless charge for a simple hearing aid so that electrical signal would be generated through detecting and receiving radio frequency waves (RF). The purpose of this design is to receive wireless charge for hearing aids and basically for any electronic device which is not required to a high energy for being setup. In this study, it has been demonstrated that as the amount of radio receiving energy increases, distance of receiver from antenna should be decreased;otherwise, either maximum amount of the receiving energy, or signal power density of the transmitter should be increased. Since it is impossible to be performed, it is decided to set up an energy receiving system constructed by rectenna and charge Circuit and to adjust their parameters to provide energy requirements for a device with low-power consumption. In this paper, different components of an energy receiving system from radio frequency band have been mentioned and a diagram block has been suggested. Subsequently, input impedance of designed antenna has been adjusted by provided relations. This impedance should be adjusted with the total impedance of regarded hearing aid Circuit by which the highest amount of received signal power is transferred to the battery of hearing aids. Received signal is converted to a dc voltage by rectifier diode. Finally, by applying a voltage regulator which has been designed using a common-collector amplifier not only the output voltage is kept constant, but the power is also strengthened. The battery of the hearing aids will be charged using the obtained power and voltage.
基金supported by the National Natural Science Foundation of China(No.61106026)the Fundamental Research Funds for the Central Universities of China(No.K50511020028)
文摘This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate can resist high voltage, but whose source–gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 μm CDMOS technology. From the results, compared with the accuracy of16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover,power efficiency is up to 95% at 12 V input and 5 V output.
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
