A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
基于0.18μm CMOS工艺开发了抗总剂量辐射加固技术,制备的1.8 V NMOS器件常态性能良好,器件在500 krad(Si)剂量点时,阈值电压与关态漏电流无明显变化。研究器件的热载流子效应,采用体电流Isub/漏电流Id模型评估器件的HCI寿命,寿命达到5...基于0.18μm CMOS工艺开发了抗总剂量辐射加固技术,制备的1.8 V NMOS器件常态性能良好,器件在500 krad(Si)剂量点时,阈值电压与关态漏电流无明显变化。研究器件的热载流子效应,采用体电流Isub/漏电流Id模型评估器件的HCI寿命,寿命达到5.75年,满足在1.1 Vdd电压下工作寿命大于0.2年的规范要求。探索总剂量辐射效应与热载流子效应的耦合作用,对比辐照与非辐照器件的热载流子损伤,器件经辐照并退火后,受到的热载流子影响变弱。评估加固工艺对器件HCI可靠性的影响,结果表明场区总剂量加固工艺并不会造成热载流子损伤加剧的问题。展开更多
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
