An improved Euclidean geometry approach to design quasi-cyclic （QC） Low-density parity-check （LDPC） codes with high-rate and low error floor is presented. The constructed QC-LDPC codes with high-rate have lower er...An improved Euclidean geometry approach to design quasi-cyclic （QC） Low-density parity-check （LDPC） codes with high-rate and low error floor is presented. The constructed QC-LDPC codes with high-rate have lower error floor than the original codes. The distribution of the minimum weight codeword is analyzed, and a sufficient existence condition of the minimum weight codeword is found. Simulations show that a lot of QC-LDPC codes with lower error floor can be designed by reducing the number of the minimum weight codewords satisfying this sufficient condition.展开更多
In this paper, we focus on the design of irregular QC-LDPC code based multi-level coded modulation(MLCM) scheme by jointly optimizing the component code rate and the degree distribution of the irregular QC-LDPC compon...In this paper, we focus on the design of irregular QC-LDPC code based multi-level coded modulation(MLCM) scheme by jointly optimizing the component code rate and the degree distribution of the irregular QC-LDPC component code. Firstly, the sub-channel capacities of MLCM systems is analyzed and discussed, based on which the optimal component code rate can be obtained. Secondly, an extrinsic information transfer chart based two-stage searching algorithm is proposed to find the good irregular QC-LDPC code ensembles with optimal component code rates for their corresponding sub-channels. Finally, by constructing the irregular QC-LDPC component codes from the designed ensembles with the aim of possibly enlarging the girth and reducing the number of the shortest cycles, the designed irregular QC-LDPC code based 16QAM and 64QAM MLCM systems can achieve 0.4 dB and 1.2 dB net coding gain, respectively, compared with the recently proposed regular QC-LDPC code based 16QAM and 64QAM MLCM systems.展开更多
In this paper, cyclic codes over the ring R = F ＋ uF ＋ vF ＋ uvF are discussed where the ring R is not a finite chain ring. By studying the polynomial ring Kn = （F ＋ uF ＋ vF ＋ uvF ）[x] / （x^n -1）and using the...In this paper, cyclic codes over the ring R = F ＋ uF ＋ vF ＋ uvF are discussed where the ring R is not a finite chain ring. By studying the polynomial ring Kn = （F ＋ uF ＋ vF ＋ uvF ）[x] / （x^n -1）and using the corresponding relationship between the cyclic codes in R and the ideals in Kn , cyclic codes over the ring R are characterized. Finally, a Gray-map is obtained and the image of cyclic codes in R is characterized.展开更多
The problem of Gray image of constacyclic code over finite chain ring is studied. A Gray map between codes over a finite chain ring and a finite field is defined. The Gray image of a linear constacyclic code over the ...The problem of Gray image of constacyclic code over finite chain ring is studied. A Gray map between codes over a finite chain ring and a finite field is defined. The Gray image of a linear constacyclic code over the finite chain ring is proved to be a distance invariant quasi-cyclic code over the finite field. It is shown that every code over the finite field, which is the Gray image of a cyclic code over the finite chain ring, is equivalent to a quasi-cyclic code.展开更多
围长较大的短码长准循环(QC)低密度奇偶校验(LDPC)码的显式构造对于QC-LDPC短码的理论研究与工程应用具有重要意义。首先提出一种基于成对策略的贪婪搜索算法,并根据此算法在列重J为4时的经验结果,归纳总结出一种具有双序列反序特征的...围长较大的短码长准循环(QC)低密度奇偶校验(LDPC)码的显式构造对于QC-LDPC短码的理论研究与工程应用具有重要意义。首先提出一种基于成对策略的贪婪搜索算法,并根据此算法在列重J为4时的经验结果,归纳总结出一种具有双序列反序特征的指数矩阵。随后证明了该指数矩阵对于任意行重L均对应于围长为8的QC-LDPC码。与现有的典型显式构造方法即最大公约数(GCD)方法相比,新QC-LDPC码提供的码长显著降低。最后,将指数矩阵的拆分拼接和掩膜处理技巧与新QC-LDPC码结合起来,设计出了译码性能在高信噪比区超过5G NR LDPC码的合成码。展开更多
该文基于有限多项式环的理论,提出了码长连续变化的准循环低密度奇偶校验(Quasi-Cyclic Low Density Parity Check,QC-LDPC)码的设计方法。当有限环基数大于某个门限值时,在此环内通过一定规则选择参数生成移位项,利用它们构造出的校验...该文基于有限多项式环的理论,提出了码长连续变化的准循环低密度奇偶校验(Quasi-Cyclic Low Density Parity Check,QC-LDPC)码的设计方法。当有限环基数大于某个门限值时,在此环内通过一定规则选择参数生成移位项,利用它们构造出的校验矩阵均可以达到较大的圈长(girth)值。在设计中,有限环基数为连续的整数,且基数与码长呈线性关系,因此能够在girth值不变的前提下实现码长的连续变化。该文分析并证明了该构造方法大大增加了可用的高性能QC-LDPC码数量,更好地服务于自适应链路系统。展开更多
To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC alg...To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.展开更多
A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filt...A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filtering the bad points, because the designed parity-check matrixes using these points have the short cycles in Tanner graph of codes. Then one of the best points from the residual good points of every line in the p-plane will be found, respectively. The optimal point is also singled out according to the bit error rate （BER） performance of the QC-LDPC codes at last. Explicit necessary and sufficient conditions for the QC-LDPC codes to have no short cycles are presented which are in favor of removing the bad points in the p-plane. Since preventing the short cycles also prevents the small stopping sets, the proposed construction method also leads to QC-LDPC codes with a higher stopping distance.展开更多
A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and...A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.展开更多
Low-density parity-check(LDPC)codes are not only capacity-approaching,but also greatly suitable for high-throughput implementation.Thus,they are the most popular codes for high-speed data transmission in the past two ...Low-density parity-check(LDPC)codes are not only capacity-approaching,but also greatly suitable for high-throughput implementation.Thus,they are the most popular codes for high-speed data transmission in the past two decades.Thanks to the low-density property of their parity-check matrices,the optimal maximum a posteriori probability decoding of LDPC codes can be approximated by message-passing decoding with linear complexity and highly parallel nature.Then,it reveals that the approximation has to carry on Tanner graphs without short cycles and small trapping sets.Last,it demonstrates that well-designed LDPC codes with the aid of computer simulation and asymptotic analysis tools are able to approach the channel capacity.Moreover,quasi-cyclic(QC)structure is introduced to significantly facilitate their high-throughput implementation.In fact,compared to the other capacity-approaching codes,QC-LDPC codes can provide better area-efficiency and energy-efficiency.As a result,they are widely applied in numerous communication systems,e.g.,Landsat satellites,Chang’e Chinese Lunar mission,5G mobile communications and so on.What’s more,its extension to non-binary Galois fields has been adopted as the channel coding scheme for BeiDou navigation satellite system.展开更多
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
基金supported by the Scientific Research Program Funded by Shaanxi Provincial Education Department (11JK1007)the Program for Young Teachers in Xi’an University of Posts and Telecommunications (0001286)the National Basic Research Program of China (2012CB328300)
文摘An improved Euclidean geometry approach to design quasi-cyclic （QC） Low-density parity-check （LDPC） codes with high-rate and low error floor is presented. The constructed QC-LDPC codes with high-rate have lower error floor than the original codes. The distribution of the minimum weight codeword is analyzed, and a sufficient existence condition of the minimum weight codeword is found. Simulations show that a lot of QC-LDPC codes with lower error floor can be designed by reducing the number of the minimum weight codewords satisfying this sufficient condition.
基金supported by National Natural Science Foundation of China(No.61571061)
文摘In this paper, we focus on the design of irregular QC-LDPC code based multi-level coded modulation(MLCM) scheme by jointly optimizing the component code rate and the degree distribution of the irregular QC-LDPC component code. Firstly, the sub-channel capacities of MLCM systems is analyzed and discussed, based on which the optimal component code rate can be obtained. Secondly, an extrinsic information transfer chart based two-stage searching algorithm is proposed to find the good irregular QC-LDPC code ensembles with optimal component code rates for their corresponding sub-channels. Finally, by constructing the irregular QC-LDPC component codes from the designed ensembles with the aim of possibly enlarging the girth and reducing the number of the shortest cycles, the designed irregular QC-LDPC code based 16QAM and 64QAM MLCM systems can achieve 0.4 dB and 1.2 dB net coding gain, respectively, compared with the recently proposed regular QC-LDPC code based 16QAM and 64QAM MLCM systems.
基金Supported by the Natural Science Foundation of Hubei Province (B20114410)
文摘In this paper, cyclic codes over the ring R = F ＋ uF ＋ vF ＋ uvF are discussed where the ring R is not a finite chain ring. By studying the polynomial ring Kn = （F ＋ uF ＋ vF ＋ uvF ）[x] / （x^n -1）and using the corresponding relationship between the cyclic codes in R and the ideals in Kn , cyclic codes over the ring R are characterized. Finally, a Gray-map is obtained and the image of cyclic codes in R is characterized.
基金supported by the National Natural Science Foundation of China(60773002,60672119 and 60873144)the Program for New Century Excellent Talents in University,the Scientific Research Foundation for the Returned Overseas Chinese Scholars,the Hi-Tech Research and Development Program of China(2007AA01Z472)
文摘The problem of Gray image of constacyclic code over finite chain ring is studied. A Gray map between codes over a finite chain ring and a finite field is defined. The Gray image of a linear constacyclic code over the finite chain ring is proved to be a distance invariant quasi-cyclic code over the finite field. It is shown that every code over the finite field, which is the Gray image of a cyclic code over the finite chain ring, is equivalent to a quasi-cyclic code.
文摘围长较大的短码长准循环(QC)低密度奇偶校验(LDPC)码的显式构造对于QC-LDPC短码的理论研究与工程应用具有重要意义。首先提出一种基于成对策略的贪婪搜索算法,并根据此算法在列重J为4时的经验结果,归纳总结出一种具有双序列反序特征的指数矩阵。随后证明了该指数矩阵对于任意行重L均对应于围长为8的QC-LDPC码。与现有的典型显式构造方法即最大公约数(GCD)方法相比,新QC-LDPC码提供的码长显著降低。最后,将指数矩阵的拆分拼接和掩膜处理技巧与新QC-LDPC码结合起来,设计出了译码性能在高信噪比区超过5G NR LDPC码的合成码。
文摘该文基于有限多项式环的理论,提出了码长连续变化的准循环低密度奇偶校验(Quasi-Cyclic Low Density Parity Check,QC-LDPC)码的设计方法。当有限环基数大于某个门限值时,在此环内通过一定规则选择参数生成移位项,利用它们构造出的校验矩阵均可以达到较大的圈长(girth)值。在设计中,有限环基数为连续的整数,且基数与码长呈线性关系,因此能够在girth值不变的前提下实现码长的连续变化。该文分析并证明了该构造方法大大增加了可用的高性能QC-LDPC码数量,更好地服务于自适应链路系统。
基金the National Key Research and Development Program of China(2019YFB1803600)the Key Scientific Research Program of Shaanxi Provincial Department of Education(22JY059)the China Civil Aviation Airworthiness Center Open Foundation(SH2021111903)。
文摘To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.
基金supported by the National Natural Science Foundation of China (60572093)Specialized Research Fund for the Doctoral Program of Higher Education (20050004016)
文摘A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filtering the bad points, because the designed parity-check matrixes using these points have the short cycles in Tanner graph of codes. Then one of the best points from the residual good points of every line in the p-plane will be found, respectively. The optimal point is also singled out according to the bit error rate （BER） performance of the QC-LDPC codes at last. Explicit necessary and sufficient conditions for the QC-LDPC codes to have no short cycles are presented which are in favor of removing the bad points in the p-plane. Since preventing the short cycles also prevents the small stopping sets, the proposed construction method also leads to QC-LDPC codes with a higher stopping distance.
基金Supported by the National Key Basic Research Program (973) Project (No. 2010CB328300)the 111 Project (No. B08038)
文摘A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.
基金supported in part by the National Natural Science Foundation of China(No.62071026,No.62201152 and No.61941106)the Natural Science Foundation of Fujian Province(No.2021J05034)Key Project of Science and Technology Innovation of Fujian Province(No.2021G02006)。
文摘Low-density parity-check(LDPC)codes are not only capacity-approaching,but also greatly suitable for high-throughput implementation.Thus,they are the most popular codes for high-speed data transmission in the past two decades.Thanks to the low-density property of their parity-check matrices,the optimal maximum a posteriori probability decoding of LDPC codes can be approximated by message-passing decoding with linear complexity and highly parallel nature.Then,it reveals that the approximation has to carry on Tanner graphs without short cycles and small trapping sets.Last,it demonstrates that well-designed LDPC codes with the aid of computer simulation and asymptotic analysis tools are able to approach the channel capacity.Moreover,quasi-cyclic(QC)structure is introduced to significantly facilitate their high-throughput implementation.In fact,compared to the other capacity-approaching codes,QC-LDPC codes can provide better area-efficiency and energy-efficiency.As a result,they are widely applied in numerous communication systems,e.g.,Landsat satellites,Chang’e Chinese Lunar mission,5G mobile communications and so on.What’s more,its extension to non-binary Galois fields has been adopted as the channel coding scheme for BeiDou navigation satellite system.
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
