This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)fu...This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.展开更多
网络的管理与监测是网络领域的重要话题,这一领域的相关技术通常也称为网络测量(network measurement).网络重要流检测(network heavy hitter detection)是网络测量的一项关键技术,也是研究对象.重要流指占用网络资源(如带宽或发送的数...网络的管理与监测是网络领域的重要话题,这一领域的相关技术通常也称为网络测量(network measurement).网络重要流检测(network heavy hitter detection)是网络测量的一项关键技术,也是研究对象.重要流指占用网络资源(如带宽或发送的数据包数量)超过某一给定标准的流,检测重要流有助于快速识别网络异常,提升网络运行效率,但链路的高速化为其实现带来了挑战.按出现时间顺序,可将重要流检测方法划分为两大类:基于传统网络框架的和基于软件定义网络(SDN)框架的.围绕网络重要流检测相关的框架与算法,系统地总结其发展过程与研究现状,并尝试给出其未来可能的发展方向.展开更多
Dynamic bandwidth allocation(DBA)is a fundamental challenge in the realm of networking.The rapid,accurate,and fair allocation of bandwidth is crucial for network service providers to fulfill service-level agreements,a...Dynamic bandwidth allocation(DBA)is a fundamental challenge in the realm of networking.The rapid,accurate,and fair allocation of bandwidth is crucial for network service providers to fulfill service-level agreements,alleviate link congestion,and devise strategies to counter network attacks.However,existing bandwidth allocation algorithms operate mainly on the control plane of the software-defined networking paradigm,which can lead to considerable probing overhead and convergence latency.Moreover,contemporary network architectures necessitate a hierarchical bandwidth allocation system that addresses latency requirements.We introduce a finegrained,hierarchical,and scalable DBA algorithm,i.e.,the HSDBA algorithm,implemented on the programmable data plane.This algorithm reduces network overhead and latency between the data plane and the controller,and it is proficient in dynamically adding and removing network configurations.We investigate the practicality of HSDBA using protocol-oblivious forwarding switches.Experimental results show that HSDBA achieves fair bandwidth allocation and isolation guarantee within approximately 25 packets.It boasts a convergence speed 0.5times higher than that of the most recent algorithm,namely,approximate hierarchical allocation of bandwidth(AHAB);meanwhile,it maintains a bandwidth enforcement accuracy of 98.1%.展开更多
A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional ...A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.展开更多
The dispensing mechanism of active code is the key technology in activenetwork. Conventional capsule and programmable switch approaches have their own shortcomings. DCCANmechanism presented in this paper overcomes the...The dispensing mechanism of active code is the key technology in activenetwork. Conventional capsule and programmable switch approaches have their own shortcomings. DCCANmechanism presented in this paper overcomes their shortcomings. In this paper, capsule andprogrammable switch, approaches are introduced and their shortcomings are analyzed. The principle ofDCCAN mechanism is described. The theoretical analyses in transmission bandwidth based on DCCANmechanism and capsule approach are described, and key factors which affect the transmissionbandwidth based on DCCAN mechanism are also discussed. At the same time, the theoretical analyses inlatency based on DCCAN mechanism and capsule approach are described. The using condition of DCCANmechanism is also discussed.展开更多
The dispensing mechanism of active code is a key technology in an active network. Conventional capsule and programmable switch approaches have their own shortcomings. The DCCAN(distributed code caching for active netw...The dispensing mechanism of active code is a key technology in an active network. Conventional capsule and programmable switch approaches have their own shortcomings. The DCCAN(distributed code caching for active network) mechanism presented in this paper overcomes these shortcomings. In this paper, capsule and programmable switch approaches are introduced, and their shortcomings are analyzed. The principle of the DCCAN mechanism is described. The theory analysis in transmit width based on the DCCAN mechanism and capsule approach are described. The theory analysis shows that the DCCAN mechanism has many good characteristics and can improve the efficiency of an active network. Key factors which affect the transmit width based on the DCCAN mechanism are discussed. The using condition of the DCCAN mechanism is also discussed.展开更多
Remote direct memory access (RDMA) has become one of the state-of-the-art high-performance network technologies in datacenters. The reliable transport of RDMA is designed based on a lossless underlying network and can...Remote direct memory access (RDMA) has become one of the state-of-the-art high-performance network technologies in datacenters. The reliable transport of RDMA is designed based on a lossless underlying network and cannot endure a high packet loss rate. However, except for switch buffer overflow, there is another kind of packet loss in the RDMA network, i.e., packet corruption, which has not been discussed in depth. The packet corruption incurs long application tail latency by causing timeout retransmissions. The challenges to solving packet corruption in the RDMA network include: 1) packet corruption is inevitable with any remedial mechanisms and 2) RDMA hardware is not programmable. This paper proposes some designs which can guarantee the expected tail latency of applications with the existence of packet corruption. The key idea is controlling the occurring probabilities of timeout events caused by packet corruption through transforming timeout retransmissions into out-of-order retransmissions. We build a probabilistic model to estimate the occurrence probabilities and real effects of the corruption patterns. We implement these two mechanisms with the help of programmable switches and the zero-byte message RDMA feature. We build an ns-3 simulation and implement optimization mechanisms on our testbed. The simulation and testbed experiments show that the optimizations can decrease the flow completion time by several orders of magnitudes with less than 3% bandwidth cost at different packet corruption rates.展开更多
基金supported by the National Natural Science Foundation of China(No.62174150)the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041)。
文摘This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.
文摘网络的管理与监测是网络领域的重要话题,这一领域的相关技术通常也称为网络测量(network measurement).网络重要流检测(network heavy hitter detection)是网络测量的一项关键技术,也是研究对象.重要流指占用网络资源(如带宽或发送的数据包数量)超过某一给定标准的流,检测重要流有助于快速识别网络异常,提升网络运行效率,但链路的高速化为其实现带来了挑战.按出现时间顺序,可将重要流检测方法划分为两大类:基于传统网络框架的和基于软件定义网络(SDN)框架的.围绕网络重要流检测相关的框架与算法,系统地总结其发展过程与研究现状,并尝试给出其未来可能的发展方向.
基金Project supported by the Strategic Priority Research Program of Chinese Academy of Sciences(No.XDA031050100。
文摘Dynamic bandwidth allocation(DBA)is a fundamental challenge in the realm of networking.The rapid,accurate,and fair allocation of bandwidth is crucial for network service providers to fulfill service-level agreements,alleviate link congestion,and devise strategies to counter network attacks.However,existing bandwidth allocation algorithms operate mainly on the control plane of the software-defined networking paradigm,which can lead to considerable probing overhead and convergence latency.Moreover,contemporary network architectures necessitate a hierarchical bandwidth allocation system that addresses latency requirements.We introduce a finegrained,hierarchical,and scalable DBA algorithm,i.e.,the HSDBA algorithm,implemented on the programmable data plane.This algorithm reduces network overhead and latency between the data plane and the controller,and it is proficient in dynamically adding and removing network configurations.We investigate the practicality of HSDBA using protocol-oblivious forwarding switches.Experimental results show that HSDBA achieves fair bandwidth allocation and isolation guarantee within approximately 25 packets.It boasts a convergence speed 0.5times higher than that of the most recent algorithm,namely,approximate hierarchical allocation of bandwidth(AHAB);meanwhile,it maintains a bandwidth enforcement accuracy of 98.1%.
文摘A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.
文摘The dispensing mechanism of active code is the key technology in activenetwork. Conventional capsule and programmable switch approaches have their own shortcomings. DCCANmechanism presented in this paper overcomes their shortcomings. In this paper, capsule andprogrammable switch, approaches are introduced and their shortcomings are analyzed. The principle ofDCCAN mechanism is described. The theoretical analyses in transmission bandwidth based on DCCANmechanism and capsule approach are described, and key factors which affect the transmissionbandwidth based on DCCAN mechanism are also discussed. At the same time, the theoretical analyses inlatency based on DCCAN mechanism and capsule approach are described. The using condition of DCCANmechanism is also discussed.
文摘The dispensing mechanism of active code is a key technology in an active network. Conventional capsule and programmable switch approaches have their own shortcomings. The DCCAN(distributed code caching for active network) mechanism presented in this paper overcomes these shortcomings. In this paper, capsule and programmable switch approaches are introduced, and their shortcomings are analyzed. The principle of the DCCAN mechanism is described. The theory analysis in transmit width based on the DCCAN mechanism and capsule approach are described. The theory analysis shows that the DCCAN mechanism has many good characteristics and can improve the efficiency of an active network. Key factors which affect the transmit width based on the DCCAN mechanism are discussed. The using condition of the DCCAN mechanism is also discussed.
基金This work was supported by the Key-Area Research and Development Program of Guangdong Province of China under Grant No.2020B0101390001the National Natural Science Foundation of China under Grant Nos.61772265 and 62072228the Fundamental Research Funds for the Central Universities of China,the Collaborative Innovation Center of Novel Software Technology and Industrialization of Jiangsu Province of China,and the Jiangsu Innovation and Entrepreneurship(Shuangchuang)Program of China.
文摘Remote direct memory access (RDMA) has become one of the state-of-the-art high-performance network technologies in datacenters. The reliable transport of RDMA is designed based on a lossless underlying network and cannot endure a high packet loss rate. However, except for switch buffer overflow, there is another kind of packet loss in the RDMA network, i.e., packet corruption, which has not been discussed in depth. The packet corruption incurs long application tail latency by causing timeout retransmissions. The challenges to solving packet corruption in the RDMA network include: 1) packet corruption is inevitable with any remedial mechanisms and 2) RDMA hardware is not programmable. This paper proposes some designs which can guarantee the expected tail latency of applications with the existence of packet corruption. The key idea is controlling the occurring probabilities of timeout events caused by packet corruption through transforming timeout retransmissions into out-of-order retransmissions. We build a probabilistic model to estimate the occurrence probabilities and real effects of the corruption patterns. We implement these two mechanisms with the help of programmable switches and the zero-byte message RDMA feature. We build an ns-3 simulation and implement optimization mechanisms on our testbed. The simulation and testbed experiments show that the optimizations can decrease the flow completion time by several orders of magnitudes with less than 3% bandwidth cost at different packet corruption rates.
