This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling tim...This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.展开更多
A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of ...A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.展开更多
基金supported by the Special Funds for State Key Development for Basic Research of China (No. 2006CB921201)the National Natural Science Foundation of China (No. 90607007)
文摘This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.
基金Supported by the National Natural Science Foundation of China(61604109)the National High-Tech R&D Program of China(2015AA042605)
文摘A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.
