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基于程序切片的电路提取技术 被引量:3
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作者 朱丹 李暾 +2 位作者 万海 郭阳 李思昆 《国防科技大学学报》 EI CAS CSCD 北大核心 2003年第6期10-15,共6页
从HDL设计描述中提取电路在VLSI设计验证、低功耗分析、测试生成等方面有广泛的应用需求。提出了一种采用程序切片技术实现的新的电路提取方法,并深入论述了基于程序切片技术从Verilog描述中进行电路提取的理论基础。该方法可以为每一... 从HDL设计描述中提取电路在VLSI设计验证、低功耗分析、测试生成等方面有广泛的应用需求。提出了一种采用程序切片技术实现的新的电路提取方法,并深入论述了基于程序切片技术从Verilog描述中进行电路提取的理论基础。该方法可以为每一个感兴趣的信号获取其"链接切片"。与以前的方法相比,该方法的优点是细粒度的、不受书写格式的限制,并且能处理更多Verilog的语法元素。该方法已经被集成到现有设计流程中,实验结果表明其方便、高效,有良好的通用性。 展开更多
关键词 程序切片 链接切片 进程依赖图 电路提取
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Automatic Circuit Extractor for HDL Description Using Program Slicing 被引量:1
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作者 TunLi YangGuo Si-KunLi 《Journal of Computer Science & Technology》 SCIE EI CSCD 2004年第5期718-728,共11页
Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation,... Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain, it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach. 展开更多
关键词 program slicing chaining slice process dependence graph circuit extraction VLSI functional verification
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