A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitation...A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.展开更多
An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and...An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.展开更多
设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与...设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与之对应的最优单元电容值1.59 f F.为了减小输入共模电压变化引起的信号敏感性失调,设计了改进的P型输入动态预放大锁存比较器,比较器采用共源共栅结构（cascode）作为P型预放大器的偏置,从而增加了预放大器的共模抑制比（CMRR）.模数转换器采用1层多晶硅8层金属（1P8M）55 nm互补型金属氧化物半导体（CMOS）工艺进行了流片验证,在1.3 V电压和100 MS/s采样率的环境下进行测试,信噪失真比（SNDR）的值为59.8 d B,功耗为1.67 mW,有效电路面积仅为0.016 2 mm^2.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61106024)the Natural Science Foundation of Jiangsu Provice,China(No.BK2010411)
文摘A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.
基金Project supported by the National Natural science Foundation of China(Nos.60725415,60971066)
文摘An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.
文摘设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与之对应的最优单元电容值1.59 f F.为了减小输入共模电压变化引起的信号敏感性失调,设计了改进的P型输入动态预放大锁存比较器,比较器采用共源共栅结构（cascode）作为P型预放大器的偏置,从而增加了预放大器的共模抑制比（CMRR）.模数转换器采用1层多晶硅8层金属（1P8M）55 nm互补型金属氧化物半导体（CMOS）工艺进行了流片验证,在1.3 V电压和100 MS/s采样率的环境下进行测试,信噪失真比（SNDR）的值为59.8 d B,功耗为1.67 mW,有效电路面积仅为0.016 2 mm^2.
