A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-p...A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.展开更多
为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步...为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步基准信号,针对网压频率异常波动,快速同步校正PWM载波周期,保证了各单元之间移相角的准确性,获得最优谐波对消效果。同时,该策略对电网谐波和幅值异常跳变不敏感,具有良好的抗干扰性和自适应性。最后通过半实物仿真和地面联调试验,验证了该策略的可行性和对谐波抑制的有效性。展开更多
A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-contr...A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.展开更多
基金The National High Technology Research and Devel-opment Program of China (863Program) (No2001AA312010)
文摘A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.
文摘为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步基准信号,针对网压频率异常波动,快速同步校正PWM载波周期,保证了各单元之间移相角的准确性,获得最优谐波对消效果。同时,该策略对电网谐波和幅值异常跳变不敏感,具有良好的抗干扰性和自适应性。最后通过半实物仿真和地面联调试验,验证了该策略的可行性和对谐波抑制的有效性。
基金Project supported by the National High-Tech Research and Development Program of China(No.2013AA014101)
文摘A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.
