The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The pro...The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The proposed digital isolator is fabricated by the 0.18 μm CMOS process. A test chip can achieve a 1 MHz signal bandwidth, a 40 ns propagation delay, a 35.5 mW input power and a 50 mA drive output current. The proposed digital isolator is pin-compatible, of small volume and low power replacement for the common 4-port optocoupler.展开更多
A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-sou...A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.展开更多
A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output im...A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm;.展开更多
文摘设计了一个2 GHz全集成的CMOS功率放大器(PA),该PA的匹配网络采用片上变压器实现,片上变压器用来实现单端信号和差分信号之间的转换和输入、输出端的阻抗匹配。采用ADS Momentum软件对片上变压器进行电磁仿真,在2 GHz频点,输入、级间和输出变压器的功率传输效率分别为74.2%,75.5%和78.4%。该PA基于TSMC 65 nm CMOS模型设计,采用Agilent ADS软件进行电路仿真,仿真结果表明:在2.5 V供电电压、2 GHz工作频率点,PA的输入、输出完全匹配到50Ω(S11=–22.4 d B、S22=–13.5 d B),功率增益为33.2 d B,最高输出功率达到23.4 d Bm,最高功率附加效率(PAE)达到35.3%,芯片面积仅为1.01 mm2。
文摘The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The proposed digital isolator is fabricated by the 0.18 μm CMOS process. A test chip can achieve a 1 MHz signal bandwidth, a 40 ns propagation delay, a 35.5 mW input power and a 50 mA drive output current. The proposed digital isolator is pin-compatible, of small volume and low power replacement for the common 4-port optocoupler.
文摘A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm;.
